From: Brian Norris <computersforpeace@gmail.com>
To: Ray Jui <rjui@broadcom.com>
Cc: Clay McClure <clay@daemons.net>,
linux-mtd@lists.infradead.org,
Florian Fainelli <f.fainelli@gmail.com>,
Scott Branden <sbranden@broadcom.com>,
bcm-kernel-feedback-list@broadcom.com
Subject: Re: [PATCH] mtd: brcmnand: Fix NAND_CMD_PARAM byte order
Date: Fri, 23 Oct 2015 18:15:47 -0700 [thread overview]
Message-ID: <20151024011547.GX13239@google.com> (raw)
In-Reply-To: <20151024011219.GW13239@google.com>
On Fri, Oct 23, 2015 at 06:12:19PM -0700, Brian Norris wrote:
> On Fri, Oct 23, 2015 at 05:48:11PM -0700, Ray Jui wrote:
> > If so, then should the logic here be the following?
> >
> > ret = cpu_to_le32(ctrl->flash_cache[offs >> 2]) >> ((offs & 0x03) << 3);
>
> I guess so, but that's getting even uglier, not prettier.
Sorry, I misread. No, that will break brcmstb too. The logic as-is is
tested and works for little endian BCM7xxx MIPS and ARM, regardless of
theory. You'll need to figure out the quirks of why/how it's really
*supposed* to work (and then to write good code around that) to get more
platforms to work with it.
Brian
next prev parent reply other threads:[~2015-10-24 1:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-23 19:47 [PATCH] mtd: brcmnand: Fix NAND_CMD_PARAM byte order Clay McClure
2015-10-23 23:27 ` Brian Norris
2015-10-24 0:48 ` Ray Jui
2015-10-24 1:12 ` Brian Norris
2015-10-24 1:15 ` Brian Norris [this message]
[not found] ` <CAOVqfW-1YurDwJbKDgUJdQZVxJ_rWDg-x+28++SZtg-vPO4kYg@mail.gmail.com>
2015-10-26 18:14 ` Brian Norris
2015-10-26 18:52 ` Ray Jui
2015-10-26 20:08 ` Clay McClure
2015-10-27 20:40 ` Brian Norris
2015-10-27 20:55 ` Ray Jui
2015-11-02 23:05 ` Clay McClure
2015-11-04 2:04 ` Brian Norris
2015-11-05 0:37 ` Ray Jui
2015-11-02 23:10 ` Clay McClure
2015-11-02 23:30 ` Brian Norris
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