From: Will Deacon <will.deacon@arm.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Ingo Molnar <mingo@kernel.org>,
"Paul E. McKenney" <paulmck@linux.vnet.ibm.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Oleg Nesterov <oleg@redhat.com>,
Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>
Subject: Re: Q: schedule() and implied barriers on arm64
Date: Wed, 28 Oct 2015 10:39:37 +0000 [thread overview]
Message-ID: <20151028103815.GA29512@arm.com> (raw)
In-Reply-To: <20151027184020.GB3201@worktop.amr.corp.intel.com>
On Tue, Oct 27, 2015 at 07:40:20PM +0100, Peter Zijlstra wrote:
> On Tue, Oct 27, 2015 at 04:19:48PM +0000, Will Deacon wrote:
> > ... and the 'normal' code will have a control hazard somewhere, followed
> > by the implicit ISB in exception return, so there's a barrier of sorts
> > there too.
>
> Which exception return?
The return to userspace after the interrupt/fault/system call that got us
into the kernel.
> > The problem is that people say "full barrier" without defining what it
> > really means, and we end up going round the houses on things like
> > transitivity (which ctrl + isb doesn't always give you).
>
> I pretty much meant smp_mb() here :-)
In which case, we don't provide the transitivity guarantees that you would
get from an smp_mb().
Will
next prev parent reply other threads:[~2015-10-28 10:39 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-16 15:18 Q: schedule() and implied barriers on arm64 Peter Zijlstra
2015-10-16 16:04 ` Paul E. McKenney
2015-10-16 16:16 ` Peter Zijlstra
2015-10-16 16:28 ` Paul E. McKenney
2015-10-16 16:39 ` Peter Zijlstra
2015-10-16 16:55 ` Catalin Marinas
2015-10-16 17:28 ` Paul E. McKenney
2015-10-16 19:07 ` Peter Zijlstra
2015-10-16 19:20 ` Paul E. McKenney
2015-10-19 15:18 ` Catalin Marinas
2015-10-16 19:06 ` Peter Zijlstra
2015-10-19 7:06 ` Ingo Molnar
2015-10-19 9:04 ` Peter Zijlstra
2015-10-19 15:21 ` Catalin Marinas
2015-10-19 16:24 ` Peter Zijlstra
2015-10-20 8:37 ` Ingo Molnar
2015-10-27 16:19 ` Will Deacon
2015-10-27 18:40 ` Peter Zijlstra
2015-10-28 10:39 ` Will Deacon [this message]
2015-10-16 17:11 ` Catalin Marinas
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