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From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-pwm@vger.kernel.org, Qipeng Zha <qipeng.zha@intel.com>,
	Huiquan Zhong <huiquan.zhong@intel.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] pwm: lpss: Add support for multiple PWMs
Date: Fri, 6 Nov 2015 11:15:55 +0200	[thread overview]
Message-ID: <20151106091555.GW1509@lahna.fi.intel.com> (raw)
In-Reply-To: <1445349187-114759-1-git-send-email-mika.westerberg@linux.intel.com>

On Tue, Oct 20, 2015 at 04:53:05PM +0300, Mika Westerberg wrote:
> New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI)
> device. Each PWM has 1k of register space allocated from the parent device.
> Add support for this.

Hi Thierry,

Are you going to pick these up to PWM tree?

Thanks.

  parent reply	other threads:[~2015-11-06  9:15 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-20 13:53 [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
2015-10-20 13:53 ` [PATCH 2/3] pwm: lpss: Support all four PWMs on Intel Broxton Mika Westerberg
2015-10-20 13:53 ` [PATCH 3/3] pwm: lpss: Add more Intel Broxton IDs Mika Westerberg
2015-11-06  9:15 ` Mika Westerberg [this message]
2015-11-06 13:29 ` [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Thierry Reding
2015-11-06 13:36   ` Mika Westerberg

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