From: Borislav Petkov <bp@alien8.de>
To: Tony Luck <tony.luck@intel.com>
Cc: "Chen, Gong" <gong.chen@linux.intel.com>,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/2] x86/mce: Make usable address checks Intel-only
Date: Sat, 21 Nov 2015 20:18:17 +0100 [thread overview]
Message-ID: <20151121191817.GD15172@pd.tnic> (raw)
In-Reply-To: <20151121191556.GB15172@pd.tnic>
From: Borislav Petkov <bp@suse.de>
Date: Sat, 21 Nov 2015 19:52:39 +0100
Subject: [PATCH 2/2] x86/mce: Make usable address checks Intel-only
The MCi_MISC bitfield definitions mce_usable_address() checks are
Intel-only. Make them so.
While at it, move mce_usable_address() up, before all its callers and
get rid of the forward declaration.
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/kernel/cpu/mcheck/mce.c | 40 ++++++++++++++++++++++------------------
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index e00e85ab7387..3865e95cc5ec 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -114,7 +114,6 @@ static struct work_struct mce_work;
static struct irq_work mce_irq_work;
static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
-static int mce_usable_address(struct mce *m);
/*
* CPU/chipset specific EDAC code can register a notifier call here to print
@@ -475,6 +474,28 @@ static void mce_report_event(struct pt_regs *regs)
irq_work_queue(&mce_irq_work);
}
+/*
+ * Check if the address reported by the CPU is in a format we can parse.
+ * It would be possible to add code for most other cases, but all would
+ * be somewhat complicated (e.g. segment offset would require an instruction
+ * parser). So only support physical addresses up to page granuality for now.
+ */
+static int mce_usable_address(struct mce *m)
+{
+ if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
+ return 0;
+
+ /* Checks after this one are Intel-specific: */
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ return 1;
+
+ if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
+ return 0;
+ if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
+ return 0;
+ return 1;
+}
+
static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
void *data)
{
@@ -930,23 +951,6 @@ reset:
return ret;
}
-/*
- * Check if the address reported by the CPU is in a format we can parse.
- * It would be possible to add code for most other cases, but all would
- * be somewhat complicated (e.g. segment offset would require an instruction
- * parser). So only support physical addresses up to page granuality for now.
- */
-static int mce_usable_address(struct mce *m)
-{
- if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
- return 0;
- if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
- return 0;
- if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
- return 0;
- return 1;
-}
-
static void mce_clear_state(unsigned long *toclear)
{
int i;
--
2.3.5
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
next prev parent reply other threads:[~2015-11-21 19:18 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-11 15:16 [PATCH] Cleanup useless codes in CMCI handler Chen, Gong
2015-11-11 19:38 ` Luck, Tony
2015-11-11 22:01 ` [UNTESTED PATCH] x86, mce: Avoid double entry of deferred errors into the genpool Tony Luck
2015-11-12 16:12 ` Chen, Gong
2015-11-19 16:15 ` Borislav Petkov
2015-11-19 19:33 ` Luck, Tony
2015-11-19 20:39 ` Borislav Petkov
2015-11-23 17:59 ` Borislav Petkov
2015-11-21 19:15 ` Borislav Petkov
2015-11-21 19:17 ` [PATCH 1/2] x86/mce: Add the missing memory error check on AMD Borislav Petkov
2015-11-21 19:18 ` Borislav Petkov [this message]
2015-11-24 0:19 ` [UNTESTED PATCH] x86, mce: Avoid double entry of deferred errors into the genpool Luck, Tony
2015-11-24 7:36 ` Borislav Petkov
2015-11-24 15:51 ` Luck, Tony
2015-11-24 18:56 ` Borislav Petkov
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