From: Ingo Molnar <mingo@kernel.org>
To: Juergen Gross <jgross@suse.com>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
the arch/x86 maintainers <x86@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>, Borislav Petkov <bp@suse.de>
Subject: Re: lapic_suspend/lapic_resume wrong?
Date: Mon, 23 Nov 2015 09:01:20 +0100 [thread overview]
Message-ID: <20151123080120.GA20696@gmail.com> (raw)
In-Reply-To: <5652C472.1010201@suse.com>
* Juergen Gross <jgross@suse.com> wrote:
> Hi,
>
> while trying to find the reason for a hanging kernel during resume
> handling I found a strange inconsistency in arch/x86/kernel/apic/apic.c
> regarding usage of config options.
>
> Attached patch addresses this, no test done as I'm not sure whether
> this is a correct approach. Can you have a look at it, please?
>
>
> Juergen
>
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index 2f69e3b..bc06c9d 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -2270,6 +2270,7 @@ static struct {
> unsigned int apic_tmict;
> unsigned int apic_tdcr;
> unsigned int apic_thmr;
> + unsigned int apic_cmci;
> } apic_pm_state;
>
> static int lapic_suspend(void)
> @@ -2299,6 +2300,10 @@ static int lapic_suspend(void)
> if (maxlvt >= 5)
> apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
> #endif
> +#ifdef CONFIG_X86_MCE_INTEL
> + if (maxlvt >= 6)
> + apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
> +#endif
>
> local_irq_save(flags);
> disable_local_APIC();
> @@ -2355,10 +2360,14 @@ static void lapic_resume(void)
> apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
> apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
> apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
> -#if defined(CONFIG_X86_MCE_INTEL)
> +#if defined(CONFIG_X86_THERMAL_VECTOR)
> if (maxlvt >= 5)
> apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
> #endif
> +#if defined(CONFIG_X86_MCE_INTEL)
> + if (maxlvt >= 6)
> + apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
> +#endif
> if (maxlvt >= 4)
> apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
> apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
the x86 bit looks absolutely sensible to me.
Have you checked whether we indeed lose this value over S/R, or is this mostly
working fine by accident, due to us executing the CMCI vector initialization via:
mce_syscore_resume()->__mcheck_cpu_init_vendor()->mce_intel_feature_init()->intel_init_cmci()
on every resume event?
The Xen fix is unrelated, just put into the same patch, right?
Thanks,
Ingo
next prev parent reply other threads:[~2015-11-23 8:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-23 7:46 lapic_suspend/lapic_resume wrong? Juergen Gross
2015-11-23 8:01 ` Ingo Molnar [this message]
2015-11-23 9:32 ` Juergen Gross
2015-11-23 9:50 ` Borislav Petkov
2015-11-23 9:57 ` Juergen Gross
2015-11-24 4:16 ` kbuild test robot
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