diff for duplicates of <20151123152158.483aa6b5@xhacker> diff --git a/a/1.txt b/N1/1.txt index 73b7d1b..31b8df3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,86 +5,83 @@ Sebastian Hesselbarth wrote: > On 20.11.2015 09:42, Jisheng Zhang wrote: > > Add syspll, mempll, cpupll, gateclk and berlin-clk nodes. -> >=20 +> > > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> > > --- -> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++= -++++++++ +> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) -> >=20 -> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/bo= -ot/dts/marvell/berlin4ct.dtsi +> > +> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > index a4a1876..808a997 100644 > > --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > @@ -42,6 +42,7 @@ > > * OTHER DEALINGS IN THE SOFTWARE. > > */ -> > =20 +> > > > +#include <dt-bindings/clock/berlin4ct.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> -> > =20 +> > > > / { > > @@ -135,6 +136,22 @@ -> > interrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_= -HIGH)>; +> > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > }; -> > =20 +> > > > + cpupll: cpupll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0x922000 0x14>, <0xea0710 4>; -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>, <&clk CLK_CPUFASTREF>; -> > + bypass-shift =3D /bits/ 8 <2>; +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0x922000 0x14>, <0xea0710 4>; +> > + #clock-cells = <0>; +> > + clocks = <&osc>, <&clk CLK_CPUFASTREF>; +> > + bypass-shift = /bits/ 8 <2>; > > + }; > > + > > + mempll: mempll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0x940034 0x14>, <0xea0710 4>; =20 ->=20 +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0x940034 0x14>, <0xea0710 4>; +> > Whenever you see overlapping/repeating reg ranges, e.g. <0xea0710 4> > you can be sure you are not representing HW structure but driver > structure here. ->=20 +> > Please merge clocks/gates/plls to a single clock complex node > and deal with the internals by using "simple-mfd" and "syscon" regmaps. ->=20 -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>, <&clk CLK_MEMFASTREF>; -> > + bypass-shift =3D /bits/ 8 <1>; +> +> > + #clock-cells = <0>; +> > + clocks = <&osc>, <&clk CLK_MEMFASTREF>; +> > + bypass-shift = /bits/ 8 <1>; > > + }; > > + -> > apb@e80000 { -> > compatible =3D "simple-bus"; -> > #address-cells =3D <1>; +> > apb at e80000 { +> > compatible = "simple-bus"; +> > #address-cells = <1>; > > @@ -225,6 +242,27 @@ > > }; > > }; -> > =20 +> > > > + syspll: syspll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0xea0200 0x14>, <0xea0710 4>; -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>; -> > + bypass-shift =3D /bits/ 8 <0>; +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0xea0200 0x14>, <0xea0710 4>; +> > + #clock-cells = <0>; +> > + clocks = <&osc>; +> > + bypass-shift = /bits/ 8 <0>; > > + }; > > + > > + gateclk: gateclk { -> > + compatible =3D "marvell,berlin4ct-gateclk"; -> > + reg =3D <0xea0700 4>; -> > + #clock-cells =3D <1>; +> > + compatible = "marvell,berlin4ct-gateclk"; +> > + reg = <0xea0700 4>; +> > + #clock-cells = <1>; > > + }; > > + > > + clk: clk { -> > + compatible =3D "marvell,berlin4ct-clk"; -> > + reg =3D <0xea0720 0x144>; =20 ->=20 +> > + compatible = "marvell,berlin4ct-clk"; +> > + reg = <0xea0720 0x144>; +> > Looking at the reg ranges, I'd say that they are all clock related > and pretty close to each other: ->=20 -> gateclk: reg =3D <0xea0700 4>; -> bypass: reg =3D <0xea0710 4>; -> clk: reg =3D <0xea0720 0x144>; +> +> gateclk: reg = <0xea0700 4>; +> bypass: reg = <0xea0710 4>; +> clk: reg = <0xea0720 0x144>; Although these ranges sit close, but we should represent HW structure as you said. @@ -92,10 +89,8 @@ said. First of all, let me describe the clks/plls in BG4CT. BG4CT contains: two kinds of PLL: normal PLL and AVPLL. These PLLs are put with their users -together. For example: mempll pll registers <0xf7940034, 0x14> is put toget= -her -with mem controller registers. AVPLL control registers are put with AV devi= -ces. +together. For example: mempll pll registers <0xf7940034, 0x14> is put together +with mem controller registers. AVPLL control registers are put with AV devices. You can also check mempll, cpupll and syspll ranges: cpupll: <0x922000 0x14> @@ -105,13 +100,10 @@ mempll: <0x940034 0x14> syspll: <0xea0200 0x14> -We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs = -use -25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypass= -ed -the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypass= -ed, -its corresponding fastrefclk is directly output to ddrphyclk/cpuclk:=20 +We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs use +25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypassed +the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypassed, +its corresponding fastrefclk is directly output to ddrphyclk/cpuclk: ---25MHZ osc----------|\ @@ -152,35 +144,32 @@ So what's the representing HW structure in fact? Here is my proposal: what do you think? -=46rom another side, let's have a look at driver/clk/mvebu. As can be seen, -different clks register are close each other, for example, gateclk and core= -clk +>From another side, let's have a look at driver/clk/mvebu. As can be seen, +different clks register are close each other, for example, gateclk and coreclk in arch/arm/boot/dts/armada-xp.dtsi. -And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, g= -t_clk -and ahb*, apb* etc...=20 +And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, gt_clk +and ahb*, apb* etc... -why these SoCs don't merge clocks/gates/plls to a single clock complex node= -?=20 +why these SoCs don't merge clocks/gates/plls to a single clock complex node? I think that's because they are representing real HW structure. Thanks, Jisheng ->=20 +> > So, please just follow the OF/driver structure we already > have for Berlin2. ->=20 +> > Sebastian ->=20 -> > + #clock-cells =3D <1>; -> > + clocks =3D <&syspll>; +> +> > + #clock-cells = <1>; +> > + clocks = <&syspll>; > > + }; > > + -> > soc_pinctrl: pin-controller@ea8000 { -> > compatible =3D "marvell,berlin4ct-soc-pinctrl"; -> > reg =3D <0xea8000 0x14>; -> > =20 ->=20 +> > soc_pinctrl: pin-controller at ea8000 { +> > compatible = "marvell,berlin4ct-soc-pinctrl"; +> > reg = <0xea8000 0x14>; +> > +> diff --git a/a/content_digest b/N1/content_digest index a745f19..8f4c57f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,24 +1,10 @@ "ref\01448008952-1787-1-git-send-email-jszhang@marvell.com\0" "ref\01448008952-1787-7-git-send-email-jszhang@marvell.com\0" "ref\0564F8B73.7070403@gmail.com\0" - "From\0Jisheng Zhang <jszhang@marvell.com>\0" - "Subject\0Re: [PATCH v2 6/6] arm64: dts: berlin4ct: add pll and clock nodes\0" + "From\0jszhang@marvell.com (Jisheng Zhang)\0" + "Subject\0[PATCH v2 6/6] arm64: dts: berlin4ct: add pll and clock nodes\0" "Date\0Mon, 23 Nov 2015 15:21:58 +0800\0" - "To\0Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" - "Cc\0<robh+dt@kernel.org>" - <pawel.moll@arm.com> - <mark.rutland@arm.com> - <ijc+devicetree@hellion.org.uk> - <galak@codeaurora.org> - <catalin.marinas@arm.com> - <will.deacon@arm.com> - <mturquette@baylibre.com> - <sboyd@codeaurora.org> - <antoine.tenart@free-electrons.com> - <devicetree@vger.kernel.org> - <linux-kernel@vger.kernel.org> - <linux-arm-kernel@lists.infradead.org> - " <linux-clk@vger.kernel.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Dear Sebastian,\n" @@ -28,86 +14,83 @@ "\n" "> On 20.11.2015 09:42, Jisheng Zhang wrote:\n" "> > Add syspll, mempll, cpupll, gateclk and berlin-clk nodes.\n" - "> >=20\n" + "> > \n" "> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>\n" "> > ---\n" - "> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++=\n" - "++++++++\n" + "> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++++++++++\n" "> > 1 file changed, 38 insertions(+)\n" - "> >=20\n" - "> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/bo=\n" - "ot/dts/marvell/berlin4ct.dtsi\n" + "> > \n" + "> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > index a4a1876..808a997 100644\n" "> > --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > @@ -42,6 +42,7 @@\n" "> > * OTHER DEALINGS IN THE SOFTWARE.\n" "> > */\n" - "> > =20\n" + "> > \n" "> > +#include <dt-bindings/clock/berlin4ct.h>\n" "> > #include <dt-bindings/interrupt-controller/arm-gic.h>\n" - "> > =20\n" + "> > \n" "> > / {\n" "> > @@ -135,6 +136,22 @@\n" - "> > \t\t\tinterrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_=\n" - "HIGH)>;\n" + "> > \t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> > \t\t};\n" - "> > =20\n" + "> > \n" "> > +\t\tcpupll: cpupll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0x922000 0x14>, <0xea0710 4>;\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>, <&clk CLK_CPUFASTREF>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <2>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0x922000 0x14>, <0xea0710 4>;\n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>, <&clk CLK_CPUFASTREF>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <2>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tmempll: mempll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0x940034 0x14>, <0xea0710 4>; =20\n" - ">=20\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0x940034 0x14>, <0xea0710 4>; \n" + "> \n" "> Whenever you see overlapping/repeating reg ranges, e.g. <0xea0710 4>\n" "> you can be sure you are not representing HW structure but driver\n" "> structure here.\n" - ">=20\n" + "> \n" "> Please merge clocks/gates/plls to a single clock complex node\n" "> and deal with the internals by using \"simple-mfd\" and \"syscon\" regmaps.\n" - ">=20\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>, <&clk CLK_MEMFASTREF>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <1>;\n" + "> \n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>, <&clk CLK_MEMFASTREF>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <1>;\n" "> > +\t\t};\n" "> > +\n" - "> > \t\tapb@e80000 {\n" - "> > \t\t\tcompatible =3D \"simple-bus\";\n" - "> > \t\t\t#address-cells =3D <1>;\n" + "> > \t\tapb at e80000 {\n" + "> > \t\t\tcompatible = \"simple-bus\";\n" + "> > \t\t\t#address-cells = <1>;\n" "> > @@ -225,6 +242,27 @@\n" "> > \t\t\t};\n" "> > \t\t};\n" - "> > =20\n" + "> > \n" "> > +\t\tsyspll: syspll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0xea0200 0x14>, <0xea0710 4>;\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <0>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0xea0200 0x14>, <0xea0710 4>;\n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <0>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tgateclk: gateclk {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin4ct-gateclk\";\n" - "> > +\t\t\treg =3D <0xea0700 4>;\n" - "> > +\t\t\t#clock-cells =3D <1>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin4ct-gateclk\";\n" + "> > +\t\t\treg = <0xea0700 4>;\n" + "> > +\t\t\t#clock-cells = <1>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tclk: clk {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin4ct-clk\";\n" - "> > +\t\t\treg =3D <0xea0720 0x144>; =20\n" - ">=20\n" + "> > +\t\t\tcompatible = \"marvell,berlin4ct-clk\";\n" + "> > +\t\t\treg = <0xea0720 0x144>; \n" + "> \n" "> Looking at the reg ranges, I'd say that they are all clock related\n" "> and pretty close to each other:\n" - ">=20\n" - "> gateclk: reg =3D <0xea0700 4>;\n" - "> bypass: reg =3D <0xea0710 4>;\n" - "> clk: reg =3D <0xea0720 0x144>;\n" + "> \n" + "> gateclk: reg = <0xea0700 4>;\n" + "> bypass: reg = <0xea0710 4>;\n" + "> clk: reg = <0xea0720 0x144>;\n" "\n" "Although these ranges sit close, but we should represent HW structure as you\n" "said.\n" @@ -115,10 +98,8 @@ "First of all, let me describe the clks/plls in BG4CT. BG4CT contains:\n" "\n" "two kinds of PLL: normal PLL and AVPLL. These PLLs are put with their users\n" - "together. For example: mempll pll registers <0xf7940034, 0x14> is put toget=\n" - "her\n" - "with mem controller registers. AVPLL control registers are put with AV devi=\n" - "ces.\n" + "together. For example: mempll pll registers <0xf7940034, 0x14> is put together\n" + "with mem controller registers. AVPLL control registers are put with AV devices.\n" "You can also check mempll, cpupll and syspll ranges:\n" "\n" "cpupll: <0x922000 0x14>\n" @@ -128,13 +109,10 @@ "syspll: <0xea0200 0x14>\n" "\n" "\n" - "We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs =\n" - "use\n" - "25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypass=\n" - "ed\n" - "the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypass=\n" - "ed,\n" - "its corresponding fastrefclk is directly output to ddrphyclk/cpuclk:=20\n" + "We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs use\n" + "25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypassed\n" + "the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypassed,\n" + "its corresponding fastrefclk is directly output to ddrphyclk/cpuclk: \n" "\n" "\n" " ---25MHZ osc----------|\\\n" @@ -175,37 +153,34 @@ "what do you think?\n" "\n" "\n" - "=46rom another side, let's have a look at driver/clk/mvebu. As can be seen,\n" - "different clks register are close each other, for example, gateclk and core=\n" - "clk\n" + ">From another side, let's have a look at driver/clk/mvebu. As can be seen,\n" + "different clks register are close each other, for example, gateclk and coreclk\n" "in arch/arm/boot/dts/armada-xp.dtsi.\n" "\n" - "And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, g=\n" - "t_clk\n" - "and ahb*, apb* etc...=20\n" + "And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, gt_clk\n" + "and ahb*, apb* etc... \n" "\n" - "why these SoCs don't merge clocks/gates/plls to a single clock complex node=\n" - "?=20\n" + "why these SoCs don't merge clocks/gates/plls to a single clock complex node? \n" "I think that's because they are representing real HW structure.\n" "\n" "Thanks,\n" "Jisheng\n" "\n" "\n" - ">=20\n" + "> \n" "> So, please just follow the OF/driver structure we already\n" "> have for Berlin2.\n" - ">=20\n" + "> \n" "> Sebastian\n" - ">=20\n" - "> > +\t\t\t#clock-cells =3D <1>;\n" - "> > +\t\t\tclocks =3D <&syspll>;\n" + "> \n" + "> > +\t\t\t#clock-cells = <1>;\n" + "> > +\t\t\tclocks = <&syspll>;\n" "> > +\t\t};\n" "> > +\n" - "> > \t\tsoc_pinctrl: pin-controller@ea8000 {\n" - "> > \t\t\tcompatible =3D \"marvell,berlin4ct-soc-pinctrl\";\n" - "> > \t\t\treg =3D <0xea8000 0x14>;\n" - "> > =20\n" - >=20 + "> > \t\tsoc_pinctrl: pin-controller at ea8000 {\n" + "> > \t\t\tcompatible = \"marvell,berlin4ct-soc-pinctrl\";\n" + "> > \t\t\treg = <0xea8000 0x14>;\n" + "> > \n" + > -bbfa7699ff7546f512800f1170d545f0e3a97f55b3223e95b223b34d4b7845e3 +8db58a9c7fd112382726b033d2a96e55720c636468d5c8b96c6e6d3f93588fab
diff --git a/a/1.txt b/N2/1.txt index 73b7d1b..a11d002 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -5,86 +5,83 @@ Sebastian Hesselbarth wrote: > On 20.11.2015 09:42, Jisheng Zhang wrote: > > Add syspll, mempll, cpupll, gateclk and berlin-clk nodes. -> >=20 +> > > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> > > --- -> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++= -++++++++ +> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) -> >=20 -> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/bo= -ot/dts/marvell/berlin4ct.dtsi +> > +> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > index a4a1876..808a997 100644 > > --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > @@ -42,6 +42,7 @@ > > * OTHER DEALINGS IN THE SOFTWARE. > > */ -> > =20 +> > > > +#include <dt-bindings/clock/berlin4ct.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> -> > =20 +> > > > / { > > @@ -135,6 +136,22 @@ -> > interrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_= -HIGH)>; +> > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > }; -> > =20 +> > > > + cpupll: cpupll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0x922000 0x14>, <0xea0710 4>; -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>, <&clk CLK_CPUFASTREF>; -> > + bypass-shift =3D /bits/ 8 <2>; +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0x922000 0x14>, <0xea0710 4>; +> > + #clock-cells = <0>; +> > + clocks = <&osc>, <&clk CLK_CPUFASTREF>; +> > + bypass-shift = /bits/ 8 <2>; > > + }; > > + > > + mempll: mempll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0x940034 0x14>, <0xea0710 4>; =20 ->=20 +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0x940034 0x14>, <0xea0710 4>; +> > Whenever you see overlapping/repeating reg ranges, e.g. <0xea0710 4> > you can be sure you are not representing HW structure but driver > structure here. ->=20 +> > Please merge clocks/gates/plls to a single clock complex node > and deal with the internals by using "simple-mfd" and "syscon" regmaps. ->=20 -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>, <&clk CLK_MEMFASTREF>; -> > + bypass-shift =3D /bits/ 8 <1>; +> +> > + #clock-cells = <0>; +> > + clocks = <&osc>, <&clk CLK_MEMFASTREF>; +> > + bypass-shift = /bits/ 8 <1>; > > + }; > > + > > apb@e80000 { -> > compatible =3D "simple-bus"; -> > #address-cells =3D <1>; +> > compatible = "simple-bus"; +> > #address-cells = <1>; > > @@ -225,6 +242,27 @@ > > }; > > }; -> > =20 +> > > > + syspll: syspll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0xea0200 0x14>, <0xea0710 4>; -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>; -> > + bypass-shift =3D /bits/ 8 <0>; +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0xea0200 0x14>, <0xea0710 4>; +> > + #clock-cells = <0>; +> > + clocks = <&osc>; +> > + bypass-shift = /bits/ 8 <0>; > > + }; > > + > > + gateclk: gateclk { -> > + compatible =3D "marvell,berlin4ct-gateclk"; -> > + reg =3D <0xea0700 4>; -> > + #clock-cells =3D <1>; +> > + compatible = "marvell,berlin4ct-gateclk"; +> > + reg = <0xea0700 4>; +> > + #clock-cells = <1>; > > + }; > > + > > + clk: clk { -> > + compatible =3D "marvell,berlin4ct-clk"; -> > + reg =3D <0xea0720 0x144>; =20 ->=20 +> > + compatible = "marvell,berlin4ct-clk"; +> > + reg = <0xea0720 0x144>; +> > Looking at the reg ranges, I'd say that they are all clock related > and pretty close to each other: ->=20 -> gateclk: reg =3D <0xea0700 4>; -> bypass: reg =3D <0xea0710 4>; -> clk: reg =3D <0xea0720 0x144>; +> +> gateclk: reg = <0xea0700 4>; +> bypass: reg = <0xea0710 4>; +> clk: reg = <0xea0720 0x144>; Although these ranges sit close, but we should represent HW structure as you said. @@ -92,10 +89,8 @@ said. First of all, let me describe the clks/plls in BG4CT. BG4CT contains: two kinds of PLL: normal PLL and AVPLL. These PLLs are put with their users -together. For example: mempll pll registers <0xf7940034, 0x14> is put toget= -her -with mem controller registers. AVPLL control registers are put with AV devi= -ces. +together. For example: mempll pll registers <0xf7940034, 0x14> is put together +with mem controller registers. AVPLL control registers are put with AV devices. You can also check mempll, cpupll and syspll ranges: cpupll: <0x922000 0x14> @@ -105,13 +100,10 @@ mempll: <0x940034 0x14> syspll: <0xea0200 0x14> -We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs = -use -25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypass= -ed -the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypass= -ed, -its corresponding fastrefclk is directly output to ddrphyclk/cpuclk:=20 +We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs use +25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypassed +the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypassed, +its corresponding fastrefclk is directly output to ddrphyclk/cpuclk: ---25MHZ osc----------|\ @@ -152,35 +144,32 @@ So what's the representing HW structure in fact? Here is my proposal: what do you think? -=46rom another side, let's have a look at driver/clk/mvebu. As can be seen, -different clks register are close each other, for example, gateclk and core= -clk +>From another side, let's have a look at driver/clk/mvebu. As can be seen, +different clks register are close each other, for example, gateclk and coreclk in arch/arm/boot/dts/armada-xp.dtsi. -And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, g= -t_clk -and ahb*, apb* etc...=20 +And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, gt_clk +and ahb*, apb* etc... -why these SoCs don't merge clocks/gates/plls to a single clock complex node= -?=20 +why these SoCs don't merge clocks/gates/plls to a single clock complex node? I think that's because they are representing real HW structure. Thanks, Jisheng ->=20 +> > So, please just follow the OF/driver structure we already > have for Berlin2. ->=20 +> > Sebastian ->=20 -> > + #clock-cells =3D <1>; -> > + clocks =3D <&syspll>; +> +> > + #clock-cells = <1>; +> > + clocks = <&syspll>; > > + }; > > + > > soc_pinctrl: pin-controller@ea8000 { -> > compatible =3D "marvell,berlin4ct-soc-pinctrl"; -> > reg =3D <0xea8000 0x14>; -> > =20 ->=20 +> > compatible = "marvell,berlin4ct-soc-pinctrl"; +> > reg = <0xea8000 0x14>; +> > +> diff --git a/a/content_digest b/N2/content_digest index a745f19..24e4ccd 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -5,20 +5,20 @@ "Subject\0Re: [PATCH v2 6/6] arm64: dts: berlin4ct: add pll and clock nodes\0" "Date\0Mon, 23 Nov 2015 15:21:58 +0800\0" "To\0Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" - "Cc\0<robh+dt@kernel.org>" - <pawel.moll@arm.com> - <mark.rutland@arm.com> - <ijc+devicetree@hellion.org.uk> - <galak@codeaurora.org> - <catalin.marinas@arm.com> - <will.deacon@arm.com> - <mturquette@baylibre.com> - <sboyd@codeaurora.org> - <antoine.tenart@free-electrons.com> - <devicetree@vger.kernel.org> - <linux-kernel@vger.kernel.org> - <linux-arm-kernel@lists.infradead.org> - " <linux-clk@vger.kernel.org>\0" + "Cc\0robh+dt@kernel.org" + pawel.moll@arm.com + mark.rutland@arm.com + ijc+devicetree@hellion.org.uk + galak@codeaurora.org + catalin.marinas@arm.com + will.deacon@arm.com + mturquette@baylibre.com + sboyd@codeaurora.org + antoine.tenart@free-electrons.com + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + linux-arm-kernel@lists.infradead.org + " linux-clk@vger.kernel.org\0" "\00:1\0" "b\0" "Dear Sebastian,\n" @@ -28,86 +28,83 @@ "\n" "> On 20.11.2015 09:42, Jisheng Zhang wrote:\n" "> > Add syspll, mempll, cpupll, gateclk and berlin-clk nodes.\n" - "> >=20\n" + "> > \n" "> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>\n" "> > ---\n" - "> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++=\n" - "++++++++\n" + "> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++++++++++\n" "> > 1 file changed, 38 insertions(+)\n" - "> >=20\n" - "> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/bo=\n" - "ot/dts/marvell/berlin4ct.dtsi\n" + "> > \n" + "> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > index a4a1876..808a997 100644\n" "> > --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > @@ -42,6 +42,7 @@\n" "> > * OTHER DEALINGS IN THE SOFTWARE.\n" "> > */\n" - "> > =20\n" + "> > \n" "> > +#include <dt-bindings/clock/berlin4ct.h>\n" "> > #include <dt-bindings/interrupt-controller/arm-gic.h>\n" - "> > =20\n" + "> > \n" "> > / {\n" "> > @@ -135,6 +136,22 @@\n" - "> > \t\t\tinterrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_=\n" - "HIGH)>;\n" + "> > \t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> > \t\t};\n" - "> > =20\n" + "> > \n" "> > +\t\tcpupll: cpupll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0x922000 0x14>, <0xea0710 4>;\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>, <&clk CLK_CPUFASTREF>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <2>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0x922000 0x14>, <0xea0710 4>;\n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>, <&clk CLK_CPUFASTREF>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <2>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tmempll: mempll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0x940034 0x14>, <0xea0710 4>; =20\n" - ">=20\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0x940034 0x14>, <0xea0710 4>; \n" + "> \n" "> Whenever you see overlapping/repeating reg ranges, e.g. <0xea0710 4>\n" "> you can be sure you are not representing HW structure but driver\n" "> structure here.\n" - ">=20\n" + "> \n" "> Please merge clocks/gates/plls to a single clock complex node\n" "> and deal with the internals by using \"simple-mfd\" and \"syscon\" regmaps.\n" - ">=20\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>, <&clk CLK_MEMFASTREF>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <1>;\n" + "> \n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>, <&clk CLK_MEMFASTREF>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <1>;\n" "> > +\t\t};\n" "> > +\n" "> > \t\tapb@e80000 {\n" - "> > \t\t\tcompatible =3D \"simple-bus\";\n" - "> > \t\t\t#address-cells =3D <1>;\n" + "> > \t\t\tcompatible = \"simple-bus\";\n" + "> > \t\t\t#address-cells = <1>;\n" "> > @@ -225,6 +242,27 @@\n" "> > \t\t\t};\n" "> > \t\t};\n" - "> > =20\n" + "> > \n" "> > +\t\tsyspll: syspll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0xea0200 0x14>, <0xea0710 4>;\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <0>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0xea0200 0x14>, <0xea0710 4>;\n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <0>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tgateclk: gateclk {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin4ct-gateclk\";\n" - "> > +\t\t\treg =3D <0xea0700 4>;\n" - "> > +\t\t\t#clock-cells =3D <1>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin4ct-gateclk\";\n" + "> > +\t\t\treg = <0xea0700 4>;\n" + "> > +\t\t\t#clock-cells = <1>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tclk: clk {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin4ct-clk\";\n" - "> > +\t\t\treg =3D <0xea0720 0x144>; =20\n" - ">=20\n" + "> > +\t\t\tcompatible = \"marvell,berlin4ct-clk\";\n" + "> > +\t\t\treg = <0xea0720 0x144>; \n" + "> \n" "> Looking at the reg ranges, I'd say that they are all clock related\n" "> and pretty close to each other:\n" - ">=20\n" - "> gateclk: reg =3D <0xea0700 4>;\n" - "> bypass: reg =3D <0xea0710 4>;\n" - "> clk: reg =3D <0xea0720 0x144>;\n" + "> \n" + "> gateclk: reg = <0xea0700 4>;\n" + "> bypass: reg = <0xea0710 4>;\n" + "> clk: reg = <0xea0720 0x144>;\n" "\n" "Although these ranges sit close, but we should represent HW structure as you\n" "said.\n" @@ -115,10 +112,8 @@ "First of all, let me describe the clks/plls in BG4CT. BG4CT contains:\n" "\n" "two kinds of PLL: normal PLL and AVPLL. These PLLs are put with their users\n" - "together. For example: mempll pll registers <0xf7940034, 0x14> is put toget=\n" - "her\n" - "with mem controller registers. AVPLL control registers are put with AV devi=\n" - "ces.\n" + "together. For example: mempll pll registers <0xf7940034, 0x14> is put together\n" + "with mem controller registers. AVPLL control registers are put with AV devices.\n" "You can also check mempll, cpupll and syspll ranges:\n" "\n" "cpupll: <0x922000 0x14>\n" @@ -128,13 +123,10 @@ "syspll: <0xea0200 0x14>\n" "\n" "\n" - "We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs =\n" - "use\n" - "25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypass=\n" - "ed\n" - "the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypass=\n" - "ed,\n" - "its corresponding fastrefclk is directly output to ddrphyclk/cpuclk:=20\n" + "We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs use\n" + "25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypassed\n" + "the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypassed,\n" + "its corresponding fastrefclk is directly output to ddrphyclk/cpuclk: \n" "\n" "\n" " ---25MHZ osc----------|\\\n" @@ -175,37 +167,34 @@ "what do you think?\n" "\n" "\n" - "=46rom another side, let's have a look at driver/clk/mvebu. As can be seen,\n" - "different clks register are close each other, for example, gateclk and core=\n" - "clk\n" + ">From another side, let's have a look at driver/clk/mvebu. As can be seen,\n" + "different clks register are close each other, for example, gateclk and coreclk\n" "in arch/arm/boot/dts/armada-xp.dtsi.\n" "\n" - "And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, g=\n" - "t_clk\n" - "and ahb*, apb* etc...=20\n" + "And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, gt_clk\n" + "and ahb*, apb* etc... \n" "\n" - "why these SoCs don't merge clocks/gates/plls to a single clock complex node=\n" - "?=20\n" + "why these SoCs don't merge clocks/gates/plls to a single clock complex node? \n" "I think that's because they are representing real HW structure.\n" "\n" "Thanks,\n" "Jisheng\n" "\n" "\n" - ">=20\n" + "> \n" "> So, please just follow the OF/driver structure we already\n" "> have for Berlin2.\n" - ">=20\n" + "> \n" "> Sebastian\n" - ">=20\n" - "> > +\t\t\t#clock-cells =3D <1>;\n" - "> > +\t\t\tclocks =3D <&syspll>;\n" + "> \n" + "> > +\t\t\t#clock-cells = <1>;\n" + "> > +\t\t\tclocks = <&syspll>;\n" "> > +\t\t};\n" "> > +\n" "> > \t\tsoc_pinctrl: pin-controller@ea8000 {\n" - "> > \t\t\tcompatible =3D \"marvell,berlin4ct-soc-pinctrl\";\n" - "> > \t\t\treg =3D <0xea8000 0x14>;\n" - "> > =20\n" - >=20 + "> > \t\t\tcompatible = \"marvell,berlin4ct-soc-pinctrl\";\n" + "> > \t\t\treg = <0xea8000 0x14>;\n" + "> > \n" + > -bbfa7699ff7546f512800f1170d545f0e3a97f55b3223e95b223b34d4b7845e3 +c3a4e787cd9ad082753aed0e814a1dc8effc0a03f6792598da05c6b928f50f85
diff --git a/a/1.txt b/N3/1.txt index 73b7d1b..a11d002 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -5,86 +5,83 @@ Sebastian Hesselbarth wrote: > On 20.11.2015 09:42, Jisheng Zhang wrote: > > Add syspll, mempll, cpupll, gateclk and berlin-clk nodes. -> >=20 +> > > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> > > --- -> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++= -++++++++ +> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) -> >=20 -> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/bo= -ot/dts/marvell/berlin4ct.dtsi +> > +> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > index a4a1876..808a997 100644 > > --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > > @@ -42,6 +42,7 @@ > > * OTHER DEALINGS IN THE SOFTWARE. > > */ -> > =20 +> > > > +#include <dt-bindings/clock/berlin4ct.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> -> > =20 +> > > > / { > > @@ -135,6 +136,22 @@ -> > interrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_= -HIGH)>; +> > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > }; -> > =20 +> > > > + cpupll: cpupll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0x922000 0x14>, <0xea0710 4>; -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>, <&clk CLK_CPUFASTREF>; -> > + bypass-shift =3D /bits/ 8 <2>; +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0x922000 0x14>, <0xea0710 4>; +> > + #clock-cells = <0>; +> > + clocks = <&osc>, <&clk CLK_CPUFASTREF>; +> > + bypass-shift = /bits/ 8 <2>; > > + }; > > + > > + mempll: mempll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0x940034 0x14>, <0xea0710 4>; =20 ->=20 +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0x940034 0x14>, <0xea0710 4>; +> > Whenever you see overlapping/repeating reg ranges, e.g. <0xea0710 4> > you can be sure you are not representing HW structure but driver > structure here. ->=20 +> > Please merge clocks/gates/plls to a single clock complex node > and deal with the internals by using "simple-mfd" and "syscon" regmaps. ->=20 -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>, <&clk CLK_MEMFASTREF>; -> > + bypass-shift =3D /bits/ 8 <1>; +> +> > + #clock-cells = <0>; +> > + clocks = <&osc>, <&clk CLK_MEMFASTREF>; +> > + bypass-shift = /bits/ 8 <1>; > > + }; > > + > > apb@e80000 { -> > compatible =3D "simple-bus"; -> > #address-cells =3D <1>; +> > compatible = "simple-bus"; +> > #address-cells = <1>; > > @@ -225,6 +242,27 @@ > > }; > > }; -> > =20 +> > > > + syspll: syspll { -> > + compatible =3D "marvell,berlin-pll"; -> > + reg =3D <0xea0200 0x14>, <0xea0710 4>; -> > + #clock-cells =3D <0>; -> > + clocks =3D <&osc>; -> > + bypass-shift =3D /bits/ 8 <0>; +> > + compatible = "marvell,berlin-pll"; +> > + reg = <0xea0200 0x14>, <0xea0710 4>; +> > + #clock-cells = <0>; +> > + clocks = <&osc>; +> > + bypass-shift = /bits/ 8 <0>; > > + }; > > + > > + gateclk: gateclk { -> > + compatible =3D "marvell,berlin4ct-gateclk"; -> > + reg =3D <0xea0700 4>; -> > + #clock-cells =3D <1>; +> > + compatible = "marvell,berlin4ct-gateclk"; +> > + reg = <0xea0700 4>; +> > + #clock-cells = <1>; > > + }; > > + > > + clk: clk { -> > + compatible =3D "marvell,berlin4ct-clk"; -> > + reg =3D <0xea0720 0x144>; =20 ->=20 +> > + compatible = "marvell,berlin4ct-clk"; +> > + reg = <0xea0720 0x144>; +> > Looking at the reg ranges, I'd say that they are all clock related > and pretty close to each other: ->=20 -> gateclk: reg =3D <0xea0700 4>; -> bypass: reg =3D <0xea0710 4>; -> clk: reg =3D <0xea0720 0x144>; +> +> gateclk: reg = <0xea0700 4>; +> bypass: reg = <0xea0710 4>; +> clk: reg = <0xea0720 0x144>; Although these ranges sit close, but we should represent HW structure as you said. @@ -92,10 +89,8 @@ said. First of all, let me describe the clks/plls in BG4CT. BG4CT contains: two kinds of PLL: normal PLL and AVPLL. These PLLs are put with their users -together. For example: mempll pll registers <0xf7940034, 0x14> is put toget= -her -with mem controller registers. AVPLL control registers are put with AV devi= -ces. +together. For example: mempll pll registers <0xf7940034, 0x14> is put together +with mem controller registers. AVPLL control registers are put with AV devices. You can also check mempll, cpupll and syspll ranges: cpupll: <0x922000 0x14> @@ -105,13 +100,10 @@ mempll: <0x940034 0x14> syspll: <0xea0200 0x14> -We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs = -use -25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypass= -ed -the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypass= -ed, -its corresponding fastrefclk is directly output to ddrphyclk/cpuclk:=20 +We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs use +25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypassed +the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypassed, +its corresponding fastrefclk is directly output to ddrphyclk/cpuclk: ---25MHZ osc----------|\ @@ -152,35 +144,32 @@ So what's the representing HW structure in fact? Here is my proposal: what do you think? -=46rom another side, let's have a look at driver/clk/mvebu. As can be seen, -different clks register are close each other, for example, gateclk and core= -clk +>From another side, let's have a look at driver/clk/mvebu. As can be seen, +different clks register are close each other, for example, gateclk and coreclk in arch/arm/boot/dts/armada-xp.dtsi. -And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, g= -t_clk -and ahb*, apb* etc...=20 +And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, gt_clk +and ahb*, apb* etc... -why these SoCs don't merge clocks/gates/plls to a single clock complex node= -?=20 +why these SoCs don't merge clocks/gates/plls to a single clock complex node? I think that's because they are representing real HW structure. Thanks, Jisheng ->=20 +> > So, please just follow the OF/driver structure we already > have for Berlin2. ->=20 +> > Sebastian ->=20 -> > + #clock-cells =3D <1>; -> > + clocks =3D <&syspll>; +> +> > + #clock-cells = <1>; +> > + clocks = <&syspll>; > > + }; > > + > > soc_pinctrl: pin-controller@ea8000 { -> > compatible =3D "marvell,berlin4ct-soc-pinctrl"; -> > reg =3D <0xea8000 0x14>; -> > =20 ->=20 +> > compatible = "marvell,berlin4ct-soc-pinctrl"; +> > reg = <0xea8000 0x14>; +> > +> diff --git a/a/content_digest b/N3/content_digest index a745f19..6d7a828 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -28,86 +28,83 @@ "\n" "> On 20.11.2015 09:42, Jisheng Zhang wrote:\n" "> > Add syspll, mempll, cpupll, gateclk and berlin-clk nodes.\n" - "> >=20\n" + "> > \n" "> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>\n" "> > ---\n" - "> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++=\n" - "++++++++\n" + "> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++++++++++\n" "> > 1 file changed, 38 insertions(+)\n" - "> >=20\n" - "> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/bo=\n" - "ot/dts/marvell/berlin4ct.dtsi\n" + "> > \n" + "> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > index a4a1876..808a997 100644\n" "> > --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi\n" "> > @@ -42,6 +42,7 @@\n" "> > * OTHER DEALINGS IN THE SOFTWARE.\n" "> > */\n" - "> > =20\n" + "> > \n" "> > +#include <dt-bindings/clock/berlin4ct.h>\n" "> > #include <dt-bindings/interrupt-controller/arm-gic.h>\n" - "> > =20\n" + "> > \n" "> > / {\n" "> > @@ -135,6 +136,22 @@\n" - "> > \t\t\tinterrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_=\n" - "HIGH)>;\n" + "> > \t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> > \t\t};\n" - "> > =20\n" + "> > \n" "> > +\t\tcpupll: cpupll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0x922000 0x14>, <0xea0710 4>;\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>, <&clk CLK_CPUFASTREF>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <2>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0x922000 0x14>, <0xea0710 4>;\n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>, <&clk CLK_CPUFASTREF>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <2>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tmempll: mempll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0x940034 0x14>, <0xea0710 4>; =20\n" - ">=20\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0x940034 0x14>, <0xea0710 4>; \n" + "> \n" "> Whenever you see overlapping/repeating reg ranges, e.g. <0xea0710 4>\n" "> you can be sure you are not representing HW structure but driver\n" "> structure here.\n" - ">=20\n" + "> \n" "> Please merge clocks/gates/plls to a single clock complex node\n" "> and deal with the internals by using \"simple-mfd\" and \"syscon\" regmaps.\n" - ">=20\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>, <&clk CLK_MEMFASTREF>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <1>;\n" + "> \n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>, <&clk CLK_MEMFASTREF>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <1>;\n" "> > +\t\t};\n" "> > +\n" "> > \t\tapb@e80000 {\n" - "> > \t\t\tcompatible =3D \"simple-bus\";\n" - "> > \t\t\t#address-cells =3D <1>;\n" + "> > \t\t\tcompatible = \"simple-bus\";\n" + "> > \t\t\t#address-cells = <1>;\n" "> > @@ -225,6 +242,27 @@\n" "> > \t\t\t};\n" "> > \t\t};\n" - "> > =20\n" + "> > \n" "> > +\t\tsyspll: syspll {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin-pll\";\n" - "> > +\t\t\treg =3D <0xea0200 0x14>, <0xea0710 4>;\n" - "> > +\t\t\t#clock-cells =3D <0>;\n" - "> > +\t\t\tclocks =3D <&osc>;\n" - "> > +\t\t\tbypass-shift =3D /bits/ 8 <0>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin-pll\";\n" + "> > +\t\t\treg = <0xea0200 0x14>, <0xea0710 4>;\n" + "> > +\t\t\t#clock-cells = <0>;\n" + "> > +\t\t\tclocks = <&osc>;\n" + "> > +\t\t\tbypass-shift = /bits/ 8 <0>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tgateclk: gateclk {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin4ct-gateclk\";\n" - "> > +\t\t\treg =3D <0xea0700 4>;\n" - "> > +\t\t\t#clock-cells =3D <1>;\n" + "> > +\t\t\tcompatible = \"marvell,berlin4ct-gateclk\";\n" + "> > +\t\t\treg = <0xea0700 4>;\n" + "> > +\t\t\t#clock-cells = <1>;\n" "> > +\t\t};\n" "> > +\n" "> > +\t\tclk: clk {\n" - "> > +\t\t\tcompatible =3D \"marvell,berlin4ct-clk\";\n" - "> > +\t\t\treg =3D <0xea0720 0x144>; =20\n" - ">=20\n" + "> > +\t\t\tcompatible = \"marvell,berlin4ct-clk\";\n" + "> > +\t\t\treg = <0xea0720 0x144>; \n" + "> \n" "> Looking at the reg ranges, I'd say that they are all clock related\n" "> and pretty close to each other:\n" - ">=20\n" - "> gateclk: reg =3D <0xea0700 4>;\n" - "> bypass: reg =3D <0xea0710 4>;\n" - "> clk: reg =3D <0xea0720 0x144>;\n" + "> \n" + "> gateclk: reg = <0xea0700 4>;\n" + "> bypass: reg = <0xea0710 4>;\n" + "> clk: reg = <0xea0720 0x144>;\n" "\n" "Although these ranges sit close, but we should represent HW structure as you\n" "said.\n" @@ -115,10 +112,8 @@ "First of all, let me describe the clks/plls in BG4CT. BG4CT contains:\n" "\n" "two kinds of PLL: normal PLL and AVPLL. These PLLs are put with their users\n" - "together. For example: mempll pll registers <0xf7940034, 0x14> is put toget=\n" - "her\n" - "with mem controller registers. AVPLL control registers are put with AV devi=\n" - "ces.\n" + "together. For example: mempll pll registers <0xf7940034, 0x14> is put together\n" + "with mem controller registers. AVPLL control registers are put with AV devices.\n" "You can also check mempll, cpupll and syspll ranges:\n" "\n" "cpupll: <0x922000 0x14>\n" @@ -128,13 +123,10 @@ "syspll: <0xea0200 0x14>\n" "\n" "\n" - "We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs =\n" - "use\n" - "25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypass=\n" - "ed\n" - "the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypass=\n" - "ed,\n" - "its corresponding fastrefclk is directly output to ddrphyclk/cpuclk:=20\n" + "We have three normal PLLS: cpupll, mempll and syspll. All these three PLLs use\n" + "25MHZ osc as clocksource. These plls can be bypassed. when syspll is bypassed\n" + "the 25MHZ osc is directly output to syspllclk. When mempll/cpupll is bypassed,\n" + "its corresponding fastrefclk is directly output to ddrphyclk/cpuclk: \n" "\n" "\n" " ---25MHZ osc----------|\\\n" @@ -175,37 +167,34 @@ "what do you think?\n" "\n" "\n" - "=46rom another side, let's have a look at driver/clk/mvebu. As can be seen,\n" - "different clks register are close each other, for example, gateclk and core=\n" - "clk\n" + ">From another side, let's have a look at driver/clk/mvebu. As can be seen,\n" + "different clks register are close each other, for example, gateclk and coreclk\n" "in arch/arm/boot/dts/armada-xp.dtsi.\n" "\n" - "And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, g=\n" - "t_clk\n" - "and ahb*, apb* etc...=20\n" + "And drivers/clk/sunxi, arch/arm/boot/dts/sun7i-a20.dtsi, the pll4, pll12, gt_clk\n" + "and ahb*, apb* etc... \n" "\n" - "why these SoCs don't merge clocks/gates/plls to a single clock complex node=\n" - "?=20\n" + "why these SoCs don't merge clocks/gates/plls to a single clock complex node? \n" "I think that's because they are representing real HW structure.\n" "\n" "Thanks,\n" "Jisheng\n" "\n" "\n" - ">=20\n" + "> \n" "> So, please just follow the OF/driver structure we already\n" "> have for Berlin2.\n" - ">=20\n" + "> \n" "> Sebastian\n" - ">=20\n" - "> > +\t\t\t#clock-cells =3D <1>;\n" - "> > +\t\t\tclocks =3D <&syspll>;\n" + "> \n" + "> > +\t\t\t#clock-cells = <1>;\n" + "> > +\t\t\tclocks = <&syspll>;\n" "> > +\t\t};\n" "> > +\n" "> > \t\tsoc_pinctrl: pin-controller@ea8000 {\n" - "> > \t\t\tcompatible =3D \"marvell,berlin4ct-soc-pinctrl\";\n" - "> > \t\t\treg =3D <0xea8000 0x14>;\n" - "> > =20\n" - >=20 + "> > \t\t\tcompatible = \"marvell,berlin4ct-soc-pinctrl\";\n" + "> > \t\t\treg = <0xea8000 0x14>;\n" + "> > \n" + > -bbfa7699ff7546f512800f1170d545f0e3a97f55b3223e95b223b34d4b7845e3 +06997a2f888a3ea5784adfa52e2950758df56b5254789bd75617ea96c5ca2ce6
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