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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id r72sm14135921pfi.0.2015.11.24.04.15.13 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 24 Nov 2015 04:15:13 -0800 (PST) Date: Tue, 24 Nov 2015 13:15:10 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20151124121510.GC12172@toto> References: <1448366481-10279-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1448366481-10279-1-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::234 Cc: Laurent Desnogues , qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Subject: Re: [Qemu-arm] [PATCH v2 for-2.5] target-arm/translate-a64.c: Correct unallocated checks for ldst_excl X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: o/XXN74evXSy On Tue, Nov 24, 2015 at 12:01:21PM +0000, Peter Maydell wrote: > The checks for the unallocated encodings in the ldst_excl group > (exclusives and load-acquire/store-release) were not correct. This > error meant that in turn we ended up with code attempting to handle > the non-existent case of "non-exclusive load-acquire/store-release > pair". Delete that broken and now unreachable code. > > Reported-by: Laurent Desnogues > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > The easiest way to validate that we have the unallocated > conditions correct now is to look at C4.4.6 "load/store exclusive" > in the v8 ARM ARM rev A.3h: our three conditions correspond > to the three "unallocated" rows in the decode table. > > v2 changes: remove incorrect comment too. > --- > target-arm/translate-a64.c | 15 ++------------- > 1 file changed, 2 insertions(+), 13 deletions(-) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index fe485a4..14e8131 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -1816,9 +1816,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, > * o2: 0 -> exclusive, 1 -> not > * o1: 0 -> single register, 1 -> register pair > * o0: 1 -> load-acquire/store-release, 0 -> not > - * > - * o0 == 0 AND o2 == 1 is un-allocated > - * o1 == 1 is un-allocated except for 32 and 64 bit sizes > */ > static void disas_ldst_excl(DisasContext *s, uint32_t insn) > { > @@ -1833,7 +1830,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) > int size = extract32(insn, 30, 2); > TCGv_i64 tcg_addr; > > - if ((!is_excl && !is_lasr) || > + if ((!is_excl && !is_pair && !is_lasr) || > + (!is_excl && is_pair) || > (is_pair && size < 2)) { > unallocated_encoding(s); > return; > @@ -1862,15 +1860,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) > } else { > do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); > } > - if (is_pair) { > - TCGv_i64 tcg_rt2 = cpu_reg(s, rt); > - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); > - if (is_store) { > - do_gpr_st(s, tcg_rt2, tcg_addr, size); > - } else { > - do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false); > - } > - } > } > } > > -- > 1.9.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35762) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a1CVD-0005Fv-9e for qemu-devel@nongnu.org; Tue, 24 Nov 2015 07:15:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a1CVA-0001Vr-47 for qemu-devel@nongnu.org; Tue, 24 Nov 2015 07:15:19 -0500 Date: Tue, 24 Nov 2015 13:15:10 +0100 From: "Edgar E. Iglesias" Message-ID: <20151124121510.GC12172@toto> References: <1448366481-10279-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1448366481-10279-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v2 for-2.5] target-arm/translate-a64.c: Correct unallocated checks for ldst_excl List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Laurent Desnogues , qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org On Tue, Nov 24, 2015 at 12:01:21PM +0000, Peter Maydell wrote: > The checks for the unallocated encodings in the ldst_excl group > (exclusives and load-acquire/store-release) were not correct. This > error meant that in turn we ended up with code attempting to handle > the non-existent case of "non-exclusive load-acquire/store-release > pair". Delete that broken and now unreachable code. > > Reported-by: Laurent Desnogues > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > The easiest way to validate that we have the unallocated > conditions correct now is to look at C4.4.6 "load/store exclusive" > in the v8 ARM ARM rev A.3h: our three conditions correspond > to the three "unallocated" rows in the decode table. > > v2 changes: remove incorrect comment too. > --- > target-arm/translate-a64.c | 15 ++------------- > 1 file changed, 2 insertions(+), 13 deletions(-) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index fe485a4..14e8131 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -1816,9 +1816,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, > * o2: 0 -> exclusive, 1 -> not > * o1: 0 -> single register, 1 -> register pair > * o0: 1 -> load-acquire/store-release, 0 -> not > - * > - * o0 == 0 AND o2 == 1 is un-allocated > - * o1 == 1 is un-allocated except for 32 and 64 bit sizes > */ > static void disas_ldst_excl(DisasContext *s, uint32_t insn) > { > @@ -1833,7 +1830,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) > int size = extract32(insn, 30, 2); > TCGv_i64 tcg_addr; > > - if ((!is_excl && !is_lasr) || > + if ((!is_excl && !is_pair && !is_lasr) || > + (!is_excl && is_pair) || > (is_pair && size < 2)) { > unallocated_encoding(s); > return; > @@ -1862,15 +1860,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) > } else { > do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); > } > - if (is_pair) { > - TCGv_i64 tcg_rt2 = cpu_reg(s, rt); > - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); > - if (is_store) { > - do_gpr_st(s, tcg_rt2, tcg_addr, size); > - } else { > - do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false); > - } > - } > } > } > > -- > 1.9.1 > >