From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.free-electrons.com (down.free-electrons.com. [37.187.137.238]) by gmr-mx.google.com with ESMTP id w187si90079wmw.1.2015.11.24.13.51.37 for ; Tue, 24 Nov 2015 13:51:37 -0800 (PST) Date: Tue, 24 Nov 2015 22:51:36 +0100 From: Alexandre Belloni To: Joshua Clayton Cc: Alessandro Zummo , rtc-linux@googlegroups.com, linux-kernel@vger.kernel.org Subject: [rtc-linux] Re: [PATCH 1/9] rtc-pcf2123: Document all registers and useful bits Message-ID: <20151124215136.GD3950@piout.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 In-Reply-To: Reply-To: rtc-linux@googlegroups.com List-ID: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , Hi, On 04/11/2015 at 07:36:32 -0800, Joshua Clayton wrote : > Document all 16 registers in the pcf2123, as well as > useful bit masks from the Control1 and seconds registers > > Signed-off-by: Joshua Clayton > --- > drivers/rtc/rtc-pcf2123.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/rtc/rtc-pcf2123.c b/drivers/rtc/rtc-pcf2123.c > index d1953bb..7756210 100644 > --- a/drivers/rtc/rtc-pcf2123.c > +++ b/drivers/rtc/rtc-pcf2123.c > @@ -47,6 +47,7 @@ > > #define DRV_VERSION "0.6" > > +/* REGISTERS */ > #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ > #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ > #define PCF2123_REG_SC (0x02) /* datetime */ > @@ -56,7 +57,27 @@ > #define PCF2123_REG_DW (0x06) > #define PCF2123_REG_MO (0x07) > #define PCF2123_REG_YR (0x08) > - > +#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ > +#define PCF2123_REG_ALRM_HR (0x0a) > +#define PCF2123_REG_ALRM_DM (0x0b) > +#define PCF2123_REG_ALRM_DW (0x0c) > +#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ > +#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ > +#define PCF2123_REG_CTDWN_TMR (0x0f) > +#define PCF2123_REG_MAX (PCF2123_REG_CTDWN_TMR) > + > +/* PCF2123_REG_CTRL1 BITS */ > +#define CTRL1_CLEAR (0x00) /* Clear */ > +#define CTRL1_CORRECTION_INT (0x02) /* Correction Interrupt */ > +#define CTRL1_12_HOUR (0x04) /* 12 hour time */ > +#define CTRL1_STOP (0x20) /* Stop the clock */ > +#define CTRL1_SW_RESET (0x58) /* Software reset */ > +#define CTRL1_EXT_TEST (0x80) /* External Clock Test mode */ > + > +/* PCF2123_REG_SC BITS */ > +#define OSC_HAS_STOPPED (0x80) /* Clock has been stopped */ > + Can you use the BIT() macro? -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- -- You received this message because you are subscribed to "rtc-linux". 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From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754683AbbKXVvl (ORCPT ); Tue, 24 Nov 2015 16:51:41 -0500 Received: from down.free-electrons.com ([37.187.137.238]:60930 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752459AbbKXVvj (ORCPT ); Tue, 24 Nov 2015 16:51:39 -0500 Date: Tue, 24 Nov 2015 22:51:36 +0100 From: Alexandre Belloni To: Joshua Clayton Cc: Alessandro Zummo , rtc-linux@googlegroups.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/9] rtc-pcf2123: Document all registers and useful bits Message-ID: <20151124215136.GD3950@piout.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 04/11/2015 at 07:36:32 -0800, Joshua Clayton wrote : > Document all 16 registers in the pcf2123, as well as > useful bit masks from the Control1 and seconds registers > > Signed-off-by: Joshua Clayton > --- > drivers/rtc/rtc-pcf2123.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/rtc/rtc-pcf2123.c b/drivers/rtc/rtc-pcf2123.c > index d1953bb..7756210 100644 > --- a/drivers/rtc/rtc-pcf2123.c > +++ b/drivers/rtc/rtc-pcf2123.c > @@ -47,6 +47,7 @@ > > #define DRV_VERSION "0.6" > > +/* REGISTERS */ > #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ > #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ > #define PCF2123_REG_SC (0x02) /* datetime */ > @@ -56,7 +57,27 @@ > #define PCF2123_REG_DW (0x06) > #define PCF2123_REG_MO (0x07) > #define PCF2123_REG_YR (0x08) > - > +#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ > +#define PCF2123_REG_ALRM_HR (0x0a) > +#define PCF2123_REG_ALRM_DM (0x0b) > +#define PCF2123_REG_ALRM_DW (0x0c) > +#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ > +#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ > +#define PCF2123_REG_CTDWN_TMR (0x0f) > +#define PCF2123_REG_MAX (PCF2123_REG_CTDWN_TMR) > + > +/* PCF2123_REG_CTRL1 BITS */ > +#define CTRL1_CLEAR (0x00) /* Clear */ > +#define CTRL1_CORRECTION_INT (0x02) /* Correction Interrupt */ > +#define CTRL1_12_HOUR (0x04) /* 12 hour time */ > +#define CTRL1_STOP (0x20) /* Stop the clock */ > +#define CTRL1_SW_RESET (0x58) /* Software reset */ > +#define CTRL1_EXT_TEST (0x80) /* External Clock Test mode */ > + > +/* PCF2123_REG_SC BITS */ > +#define OSC_HAS_STOPPED (0x80) /* Clock has been stopped */ > + Can you use the BIT() macro? -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com