[U-Boot] [PATCHv4 3/9] arm: socfpga: arria10: add reset manager for Arria10

[Marek Vasut <marex@denx.de>]

On Wednesday, December 02, 2015 at 08:31:27 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add the defines for the reset manager and some basic reset functionality.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v4: rename mod_reset names to be used by both gen5 and a10
> v3: remove duplicate reset function
>     use CONFIG_SOCFPGA_GEN5
> v2: integrate into a5/c5 reset manager
> ---
>  arch/arm/mach-socfpga/include/mach/reset_manager.h | 71
> +++++++++++++++++++++- arch/arm/mach-socfpga/reset_manager.c             
> | 36 ++++++++--- 2 files changed, 97 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> b/arch/arm/mach-socfpga/include/mach/reset_manager.h index
> e50fbd8..b34c7c6 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -15,19 +15,56 @@ void socfpga_bridges_reset(int enable);
>  void socfpga_per_reset(u32 reset, int set);
>  void socfpga_per_reset_all(void);
> 
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  struct socfpga_reset_manager {
>  	u32	status;
>  	u32	ctrl;
>  	u32	counts;
>  	u32	padding1;
>  	u32	mpu_mod_reset;
> -	u32	per_mod_reset;
> -	u32	per2_mod_reset;
> +	u32	per0_mod_reset; /* per_mod_reset */
> +	u32	per1_mod_reset; /* per2_mod_reset */
>  	u32	brg_mod_reset;
> -	u32	misc_mod_reset;
> +	u32	sys_mod_reset; /* misc_mod_reset */

OK, so why do you rename it for gen5 and not gen10 ?

>  	u32	padding2[12];
>  	u32	tstscratch;

[...]

> @@ -26,13 +28,13 @@ void socfpga_per_reset(u32 reset, int set)
>  	if (RSTMGR_BANK(reset) == 0)
>  		reg = &reset_manager_base->mpu_mod_reset;
>  	else if (RSTMGR_BANK(reset) == 1)
> -		reg = &reset_manager_base->per_mod_reset;
> +		reg = &reset_manager_base->per0_mod_reset;
>  	else if (RSTMGR_BANK(reset) == 2)
> -		reg = &reset_manager_base->per2_mod_reset;
> +		reg = &reset_manager_base->per1_mod_reset;
>  	else if (RSTMGR_BANK(reset) == 3)
>  		reg = &reset_manager_base->brg_mod_reset;
>  	else if (RSTMGR_BANK(reset) == 4)
> -		reg = &reset_manager_base->misc_mod_reset;
> +		reg = &reset_manager_base->sys_mod_reset;

This change would not be necessary than.

>  	else	/* Invalid reset register, do nothing */
>  		return;
> 
> @@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
>   * Assert reset on every peripheral but L4WD0.
>   * Watchdog must be kept intact to prevent glitches
>   * and/or hangs.
> + * For the Arria10, we disable all the peripherals except L4 watchdog0,
> + * L4 Timer 0, and ECC.
>   */
>  void socfpga_per_reset_all(void)
>  {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
> 
> -	writel(~l4wd0, &reset_manager_base->per_mod_reset);
> -	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
> +	writel(~l4wd0, &reset_manager_base->per0_mod_reset);
> +	writel(0xffffffff, &reset_manager_base->per1_mod_reset);
> +#else
> +	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
> +			(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
> +
> +	unsigned mask_ecc_ocp = 0x0000FF00;
> +
> +	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> +	writel(~l4wd0, &reset_manager_base->per1_mod_reset);
> +	setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp);
> +
> +	/* Finally disable the ECC_OCP */
> +	setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp);
> +#endif
>  }
> 
>  /*
> @@ -71,13 +89,15 @@ void reset_cpu(ulong addr)
>  		;
>  }
> 
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  /*
>   * Release peripherals from reset based on handoff
>   */
>  void reset_deassert_peripherals_handoff(void)
>  {
> -	writel(0, &reset_manager_base->per_mod_reset);
> +	writel(0, &reset_manager_base->per0_mod_reset);

And this change.

>  }
> +#endif
> 
>  #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
>  void socfpga_bridges_reset(int enable)
> @@ -92,6 +112,7 @@ void socfpga_bridges_reset(int enable)
> 
>  void socfpga_bridges_reset(int enable)
>  {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  	const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
>  				L3REGS_REMAP_HPS2FPGA_MASK |
>  				L3REGS_REMAP_OCRAM_MASK;
> @@ -116,5 +137,6 @@ void socfpga_bridges_reset(int enable)
>  		/* Remap the bridges into memory map */
>  		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
>  	}
> +#endif
>  }
>  #endif

It looks OK otherwise of course.