[U-Boot] ARMv7 MMU shareability issue

[Albert ARIBAUD <albert.u.boot@aribaud.net>]

Hello Pavel,

On Mon, 14 Dec 2015 08:48:16 +0100, Pavel Machek <pavel@denx.de> wrote:
> Hi!
> 
> > This patch has several effects:
> > 
> > - it selects proper ARMv7 translation table level 1 bit definitions;
> > - it provides proper ARMv7 definitions for WT/WB/WA;
> > - it selects proper ARMv7 settings for TTBR0.
> > 
> > All these are correct as per the docs I have (although I may have missed
> > something during the readings (and cross-readings with Marek) of these
> > last hours/days.
> > 
> > Now, one specific effect goes against performance, and it is the
> > setting of bit S in all TT entries. This bit makes the corresponding
> > region shareable, but for all I know, in U-Boot we don't have more than
> > one core accessing the same memory or registers sets so -- at least for
> > the major part of its execution -- there is no reason for any region to
> > be shareable.
> 
> Well, I'm currently working on AMP patch, which will mean two
> processors at the same time in u-boot.

Will they share memory or will they use another mechanism for sync?

> Also... we provide memory modify operations for the user. User may
> be trying to communicate with second core.
> 
> > /That/ effect I certainly don't want.
> 
> How big is the slowdown from S bit?

A 4MB memory-to-memory transfer goes from instantaneous to 2-3 seconds;
Ethernet performance drops by 40%.

> Best regards,

Amicalement,
-- 
Albert.