Re: [PATCH] drm/dp: Do not busy-loop during link training

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Dec 14, 2015 at 02:21:56PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Use microsecond sleeps for the clock recovery and channel equalization
> delays during link training. The duration of these delays can be from
> 100 us up to 16 ms. It is rude to busy-loop for that amount of time.

Do you have some numbers on how this affects a typical link training
cycle?

> 
> While at it, also convert to standard coding style by putting the
> opening braces in a function definition on a new line.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++--------
>  1 file changed, 18 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 73a3e0544f36..2dcc4efcd34c 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -125,19 +125,29 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ
>  }
>  EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
>  
> -void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> -	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
> -		udelay(100);
> +void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> +	unsigned int min;
> +
> +	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] != 0)
> +		min = dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4000;
>  	else
> -		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
> +		min = 100;
> +
> +	usleep_range(min, min * 2);
>  }
>  EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
>  
> -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> -	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
> -		udelay(400);
> +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> +	unsigned int min;
> +
> +	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] != 0)
> +		min = dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4000;
>  	else
> -		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
> +		min = 400;
> +
> +	usleep_range(min, min * 2);
>  }
>  EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>  
> -- 
> 2.5.0
> 
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-- 
Ville Syrjälä
Intel OTC
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