From: Ben Widawsky <benjamin.widawsky@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Intel GFX <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: Correct MI_STORE_DWORD_INDEX usage
Date: Tue, 15 Dec 2015 16:22:57 -0800 [thread overview]
Message-ID: <20151216002253.GA26449@intel.com> (raw)
In-Reply-To: <20151216001820.GB7574@nuc-i3427.alporthouse.com>
On Wed, Dec 16, 2015 at 12:18:20AM +0000, Chris Wilson wrote:
> On Tue, Dec 15, 2015 at 04:13:49PM -0800, Ben Widawsky wrote:
> > This has been incorrect since the original commit from Oscar Mateo here:
> > commit 4da46e1e5bb7e7396fad172cdaffbe496562f3d8
> > Author: Oscar Mateo <oscar.mateo@intel.com>
> > Date: Thu Jul 24 17:04:27 2014 +0100
> >
> > drm/i915/bdw: GEN-specific logical ring emit request
> >
> > The command's offset field is only 10 bits, and this is correct in all the other
> > add_request commands. It's highly likely this this patch makes no functional
> > difference because the hardware will hopefully ignore 31:12 anyway. Technically
> > the existing code is wrong because the docs say the upper bits are MBZ.
> > Ultimately, the patch just clears up the confusion.
> >
> > NOTE: This patch was compile tested only.
> > NOTE2: The modern docs call it MI_STORE_DATA_INDEX not MI_STORE_DWORD_INDEX
>
> It doesn't use MI_STORE_DATA_INDEX, but a write to a specific memory
> address (MI_STORE_DWORD_IMM) as it is not storing in the per-context HWS
> but a global (per-engine) page.
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
You're right. I just noticed the cmd = MI_STORE_DWORD_IMM_GEN4. Sorry about
that.
--
Ben Widawsky, Intel Open Source Technology Center
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prev parent reply other threads:[~2015-12-16 0:22 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-16 0:13 [PATCH] drm/i915: Correct MI_STORE_DWORD_INDEX usage Ben Widawsky
2015-12-16 0:18 ` Chris Wilson
2015-12-16 0:22 ` Ben Widawsky [this message]
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