From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/2] arm64: Use PoU cache instr for I/D coherency
Date: Wed, 16 Dec 2015 11:39:21 +0000 [thread overview]
Message-ID: <20151216113920.GC2765@mbp> (raw)
In-Reply-To: <1450260690-5431-3-git-send-email-ashoks@broadcom.com>
On Wed, Dec 16, 2015 at 02:11:30AM -0800, Ashok Kumar wrote:
> @@ -74,13 +79,11 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
> if (!page_mapping(page))
> return;
>
> - if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
> - __flush_dcache_area(page_address(page),
> - PAGE_SIZE << compound_order(page));
> + if (!test_and_set_bit(PG_dcache_clean, &page->flags))
> + sync_icache_aliases(page_address(page),
> + PAGE_SIZE << compound_order(page));
> + else if (icache_is_aivivt())
> __flush_icache_all();
> - } else if (icache_is_aivivt()) {
> - __flush_icache_all();
> - }
> }
You changed the original code path slightly here. We had a
__flush_icache_all() even for non-aliasing VIPT but it now does the
I-cache invalidation per page. It may be an improvement, I can't tell
without benchmarks but you should at least mention this in the commit
log so that we remember in the future. Apart from this:
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
next prev parent reply other threads:[~2015-12-16 11:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-16 10:11 [PATCH v3 0/2] arm64: change PoC D-cache flush to PoU Ashok Kumar
2015-12-16 10:11 ` [PATCH v3 1/2] arm64: Defer dcache flush in __cpu_copy_user_page Ashok Kumar
2015-12-16 10:11 ` [PATCH v3 2/2] arm64: Use PoU cache instr for I/D coherency Ashok Kumar
2015-12-16 11:39 ` Catalin Marinas [this message]
2015-12-16 12:18 ` Will Deacon
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