[U-Boot] [PATCH v1 07/18] board: Add Microchip PIC32MZ[DA] Starter Kit board.

[Marek Vasut <marex@denx.de>]

On Thursday, December 17, 2015 at 06:30:38 PM, Purna Chandra Mandal wrote:
[...]

> diff --git a/board/microchip/pic32mzda/config.mk
> b/board/microchip/pic32mzda/config.mk new file mode 100644
> index 0000000..a12e712
> --- /dev/null
> +++ b/board/microchip/pic32mzda/config.mk
> @@ -0,0 +1,4 @@
> +#
> +# Microchip PIC32MZ[DA] board (PIC32 SoC powered by MIPS M14KEc CPU)
> +#
> +CONFIG_SYS_TEXT_BASE = 0x9d004000
> diff --git a/board/microchip/pic32mzda/ddr.c
> b/board/microchip/pic32mzda/ddr.c new file mode 100644
> index 0000000..31a44fa
> --- /dev/null
> +++ b/board/microchip/pic32mzda/ddr.c
> @@ -0,0 +1,389 @@
> +/*
> + * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + *
> + */
> +
> +#include <asm/io.h>
> +#include <stdint.h>
> +#include <config.h>
> +#include <linux/kernel.h>
> +#include <asm/mipsregs.h>
> +#include <asm/arch-pic32/pic32.h>
> +
> +#include "ddr.h"
> +
> +/* macros */
> +#define hc_clk_dly(dly)        \
> +    (max_t(u32, (DIV_ROUND_UP((dly), CLK_PERIOD)), 2) - 2)
> +
> +/* Host Commands */
> +#define IDLE_NOP        0x00FFFFFF
> +#define PRECH_ALL_CMD        0x00FFF401
> +#define REF_CMD            0x00FFF801
> +#define LOAD_MODE_CMD        0x00FFF001
> +#define CKE_LOW            0x00FFEFFE
> +
> +#define NUM_HOST_CMDS        12
> +
> +/* DDR address decoding */
> +#define COL_HI_RSHFT        0
> +#define COL_HI_MASK        0
> +#define COL_LO_MASK        ((1 << COL_BITS) - 1)
> +
> +#define BA_RSHFT        COL_BITS
> +#define BANK_ADDR_MASK        ((1 << BA_BITS) - 1)
> +
> +#define ROW_ADDR_RSHIFT        (BA_RSHFT + BA_BITS)
> +#define ROW_ADDR_MASK        ((1 << ROW_BITS) - 1)
> +
> +#define CS_ADDR_RSHIFT        0
> +#define CS_ADDR_MASK        0
> +
> +/* MPLL freq is 400MHz */
> +#define CLK_PERIOD              2500    /* 2500 psec */
> +#define CTRL_CLK_PERIOD         (CLK_PERIOD * 2)
> +
> +/* Arbiter */
> +#define NUM_AGENTS              5
> +#define MIN_LIM_WIDTH           5
> +#define RQST_PERIOD_WIDTH       8
> +#define MIN_CMDACPT_WIDTH       8
> +
> +#define EN_AUTO_PRECH           0
> +#define SB_PRI                  1
> +#define BIG_ENDIAN              0
> +#define HALF_RATE_MODE          1
> +
> +/*************************************************************************
> ****/ +/* DDR definitions */
> +/*************************************************************************
> ****/ +
> +/* DDR Address Mapping: CS, ROW, BA, COL */
> +#define COL_BITS    10
> +#define ROW_BITS    13
> +#define BA_BITS        3
> +#define CS_BITS        1

OK, so how many copies of this code will we have by the end of the day ?
One for each board ? That ain't gonna work ...

> +/* DDR constants */
> +#define BL        2    /* Burst length in cycles */
> +
> +/* default CAS latency for all speed grades */
> +#define RL        5
> +
> +/* default write latency for all speed grades = CL-1 */
> +#define WL        4
> +
> +#define MAX_BURST    3
> +
> +/* NOTE: DDR data from Micron MT47H64M16HR-3 data sheet */
> +#define tRFC_MIN    127500    /* psec */
> +#define tWR        15000    /* psec */
> +#define tRP        12500    /* psec */
> +#define tRCD        12500    /* psec */
> +#define tRRD        7500    /* psec */

This is board specific, but the code is not I believe. So the common code
should go into drivers/ddr/

> +/* tRRD_TCK is a minimum of 2 clk periods, regardless of clk freq */
> +#define tRRD_TCK    2
> +#define tWTR        7500    /* psec */

[...]

> +    /* ODT Config */
> +    writel(0x00000000, DDR2ODTCFG);
> +    writel(0x00010000, DDR2ODTENCFG);/* WREN on CS */
> +
> +    writel(((RL - 3) << 8) | ((WL - 3) << 12) | (2 << 16) | (3 << 20),
> +           DDR2ODTCFG);
> +
> +    /* TODO: resolve differences in NXTDATRQDLY, NXDATAVDLY and RDATENDLY
> */ +    writel(/*(WL - 1)*/2 | (/*((RL + 1) & 0x0F)*/4  << 4) |
> +           (/*(RL - 1)*/2 << 16) |
> +           (MAX_BURST << 24) | (7 << 28) | (BIG_ENDIAN << 31),
> +           DDR2XFERCFG);

Fixme please ;-)

> +    /* DRAM Initialization */
> +    /* bring CKE high after reset and wait 400 nsec */
> +    writel(IDLE_NOP, DDR2CMD10);
> +    writel((0x00 | (0x00 << 8) | (hc_clk_dly(400000) << 11)),
> +           DDR2CMD20);
> +
> +    /* issue precharge all command */
> +    writel(PRECH_ALL_CMD, DDR2CMD10 + 0x04);
> +    writel((0x04 | (0x00 << 8) | (hc_clk_dly(tRP + CLK_PERIOD) << 11)),
> +           DDR2CMD20 + 0x04);
> +
> +    /* initialize EMR2 */
> +    writel(LOAD_MODE_CMD, DDR2CMD10 + 0x08);
> +    writel((0x00 | (0x02 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)),
> +           DDR2CMD20 + 0x08);

[...]

> +    writel(0x1B, DDR2CMDISSUE);
> +    writel(0x01, DDR2MEMCON);
> +
> +    while (readl(DDR2CMDISSUE) & 0x10)
> +        ;

Use the wait_for_bit() function here and for the other unbounded while loop 
below. This will add timeout to the wait, so your code will not get stuck in
an endless loop.

> +    writel(0x03, DDR2MEMCON);
> +
> +    /* SCL Start */
> +    writel(SCL_START | SCL_EN, DDR2SCLSTART);
> +
> +    /* Wait for SCL byte to pass */
> +    while ((readl(DDR2SCLSTART) & SCL_LUBPASS) != SCL_LUBPASS)
> +        ;
> +}
> diff --git a/board/microchip/pic32mzda/ddr.h
> b/board/microchip/pic32mzda/ddr.h new file mode 100644
> index 0000000..7828169
> --- /dev/null
> +++ b/board/microchip/pic32mzda/ddr.h
> @@ -0,0 +1,46 @@
> +/*
> + * (c) 2015 Purna Chandra Mandal purna.mandal at microchip.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + *
> + */
> +
> +#ifndef __PIC32MZDA_DDR_H
> +#define __PIC32MZDA_DDR_H
> +
> +#define DDR2TSEL    (PIC32_DDR2C_BASE + 0x00) /* ARB_AGENT_SEL       */
> +#define DDR2MINLIM    (PIC32_DDR2C_BASE + 0x04) /* MIN_LIMIT           */

Nuke the trailing indent in the comment please.

> +#define DDR2REQPRD    (PIC32_DDR2C_BASE + 0x08) /* RQST_PERIOD         */
> +#define DDR2MINCMD    (PIC32_DDR2C_BASE + 0x0c) /* MIN_CMD_ACPT        */
> +#define DDR2MEMCON    (PIC32_DDR2C_BASE + 0x10) /* MEM_START           */
> +#define DDR2MEMCFG0    (PIC32_DDR2C_BASE + 0x14) /* MEM_CONFIG_1        */
> +#define DDR2MEMCFG1    (PIC32_DDR2C_BASE + 0x18) /* MEM_CONFIG_2        */
> +#define DDR2MEMCFG2    (PIC32_DDR2C_BASE + 0x1c) /* MEM_CONFIG_3        */
> +#define DDR2MEMCFG3    (PIC32_DDR2C_BASE + 0x20) /* MEM_CONFIG_4        */
> +#define DDR2MEMCFG4    (PIC32_DDR2C_BASE + 0x24) /* MEM_CONFIG_5        */
> +#define DDR2REFCFG    (PIC32_DDR2C_BASE + 0x28) /* REF_CONFIG          */
> +#define DDR2PWRCFG    (PIC32_DDR2C_BASE + 0x2c) /* PWR_SAVE_ECC_CONFIG */
> +#define DDR2DLYCFG0    (PIC32_DDR2C_BASE + 0x30) /* DLY_CONFIG1         */
[...]