diff for duplicates of <20151218214112.GU30359@lukather> diff --git a/a/1.txt b/N1/1.txt index c210fdf..0ec0f06 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,7 +5,7 @@ On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote: > This adds the basic dtsi, the clocks differs from > earlier sun8i SOCs. > -> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> +> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 206 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 206 insertions(+) @@ -20,7 +20,7 @@ On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote: > +/* > + * Copyright 2015 Vishnu Patekar > + * -> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> +> + * Vishnu Patekar <vishnupatekar0510@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual @@ -81,25 +81,25 @@ On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu@0 { +> + cpu at 0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + -> + cpu@1 { +> + cpu at 1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + -> + cpu@2 { +> + cpu at 2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + -> + cpu@3 { +> + cpu at 3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; @@ -107,13 +107,13 @@ On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote: A \n here please -> + cpu@100 { +> + cpu at 100 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0x100>; > + }; > + -> + cpu@101 { +> + cpu at 101 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0x101>; @@ -121,13 +121,13 @@ A \n here please Ditto. -> + cpu@102 { +> + cpu at 102 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0x102>; > + }; > + -> + cpu@103 { +> + cpu at 103 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0x103>; @@ -178,7 +178,7 @@ Do you need to modify the clocks driver in your first commit then? > + #size-cells = <1>; > + ranges; > + -> + gic: interrupt-controller@01c81000 { +> + gic: interrupt-controller at 01c81000 { > + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, @@ -192,7 +192,7 @@ Please order the nodes by ascending physical addresses. > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + -> + pio: pinctrl@01c20800 { +> + pio: pinctrl at 01c20800 { > + compatible = "allwinner,sun8i-a83t-pinctrl"; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, @@ -204,7 +204,7 @@ Please order the nodes by ascending physical addresses. > + #interrupt-cells = <3>; > + #gpio-cells = <3>; > + -> + mmc0_pins_a: mmc0@0 { +> + mmc0_pins_a: mmc0 at 0 { > + allwinner,pins = "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + allwinner,function = "mmc0"; @@ -212,14 +212,14 @@ Please order the nodes by ascending physical addresses. > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart0_pins_a: uart0@0 { +> + uart0_pins_a: uart0 at 0 { > + allwinner,pins = "PF2", "PF4"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart0_pins_b: uart0@1 { +> + uart0_pins_b: uart0 at 1 { > + allwinner,pins = "PB9", "PB10"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -227,7 +227,7 @@ Please order the nodes by ascending physical addresses. > + }; > + }; > + -> + uart0: serial@01c28000 { +> + uart0: serial at 01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -246,3 +246,10 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: signature.asc +Type: application/pgp-signature +Size: 819 bytes +Desc: Digital signature +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151218/fcb0df50/attachment.sig> diff --git a/a/content_digest b/N1/content_digest index 10469a7..aff78b5 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,28 +1,10 @@ "ref\01450445451-311-1-git-send-email-vishnupatekar0510@gmail.com\0" "ref\01450445451-311-3-git-send-email-vishnupatekar0510@gmail.com\0" - "ref\01450445451-311-3-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" - "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" - "Subject\0Re: [PATCH v3 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi\0" + "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" + "Subject\0[PATCH v3 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi\0" "Date\0Fri, 18 Dec 2015 22:41:12 +0100\0" - "To\0Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" - corbet-T1hC0tSOHrs@public.gmane.org - pawel.moll-5wv7dgnIgG8@public.gmane.org - mark.rutland-5wv7dgnIgG8@public.gmane.org - ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org - galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org - emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org - linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org - hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org - wens-jdAy2FN1RRM@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org - " linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "Hi,\n" "\n" @@ -31,7 +13,7 @@ "> This adds the basic dtsi, the clocks differs from\n" "> earlier sun8i SOCs.\n" "> \n" - "> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" + "> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\n" "> ---\n" "> arch/arm/boot/dts/sun8i-a83t.dtsi | 206 ++++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 206 insertions(+)\n" @@ -46,7 +28,7 @@ "> +/*\n" "> + * Copyright 2015 Vishnu Patekar\n" "> + *\n" - "> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" + "> + * Vishnu Patekar <vishnupatekar0510@gmail.com>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -107,25 +89,25 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu@0 {\n" + "> +\t\tcpu at 0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@1 {\n" + "> +\t\tcpu at 1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@2 {\n" + "> +\t\tcpu at 2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@3 {\n" + "> +\t\tcpu at 3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -133,13 +115,13 @@ "\n" "A \\n here please\n" "\n" - "> +\t\tcpu@100 {\n" + "> +\t\tcpu at 100 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x100>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@101 {\n" + "> +\t\tcpu at 101 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x101>;\n" @@ -147,13 +129,13 @@ "\n" "Ditto.\n" "\n" - "> +\t\tcpu@102 {\n" + "> +\t\tcpu at 102 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x102>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@103 {\n" + "> +\t\tcpu at 103 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x103>;\n" @@ -204,7 +186,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tgic: interrupt-controller@01c81000 {\n" + "> +\t\tgic: interrupt-controller at 01c81000 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" "> +\t\t\treg = <0x01c81000 0x1000>,\n" "> +\t\t\t <0x01c82000 0x1000>,\n" @@ -218,7 +200,7 @@ "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl@01c20800 {\n" + "> +\t\tpio: pinctrl at 01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a83t-pinctrl\";\n" "> +\t\t\tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,\n" "> +\t\t\t\t <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -230,7 +212,7 @@ "> +\t\t\t#interrupt-cells = <3>;\n" "> +\t\t\t#gpio-cells = <3>;\n" "> +\n" - "> +\t\t\tmmc0_pins_a: mmc0@0 {\n" + "> +\t\t\tmmc0_pins_a: mmc0 at 0 {\n" "> +\t\t\t\tallwinner,pins = \"PF0\", \"PF1\", \"PF2\",\n" "> +\t\t\t\t\t\t \"PF3\", \"PF4\", \"PF5\";\n" "> +\t\t\t\tallwinner,function = \"mmc0\";\n" @@ -238,14 +220,14 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0@0 {\n" + "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0_pins_b: uart0@1 {\n" + "> +\t\t\tuart0_pins_b: uart0 at 1 {\n" "> +\t\t\t\tallwinner,pins = \"PB9\", \"PB10\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -253,7 +235,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial@01c28000 {\n" + "> +\t\tuart0: serial at 01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -271,6 +253,13 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - http://free-electrons.com + "http://free-electrons.com\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: signature.asc\n" + "Type: application/pgp-signature\n" + "Size: 819 bytes\n" + "Desc: Digital signature\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151218/fcb0df50/attachment.sig> -b0e77dd479ce33a72c26ccc52d974a63b4e6119f8aeeb59082d8708c3ee7fcbe +8a7eb083a9cfbbdd6010370b64b2206c9c0e9849fb0af9ed8c458ff81ae9a558
diff --git a/a/1.txt b/N2/1.txt index c210fdf..d4e5fe6 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -5,7 +5,7 @@ On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote: > This adds the basic dtsi, the clocks differs from > earlier sun8i SOCs. > -> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> +> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 206 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 206 insertions(+) @@ -20,7 +20,7 @@ On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote: > +/* > + * Copyright 2015 Vishnu Patekar > + * -> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> +> + * Vishnu Patekar <vishnupatekar0510@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual diff --git a/N2/2.bin b/N2/2.bin new file mode 100644 index 0000000..bc853b2 --- /dev/null +++ b/N2/2.bin @@ -0,0 +1,17 @@ +-----BEGIN PGP SIGNATURE----- +Version: GnuPG v1 + +iQIcBAEBAgAGBQJWdH14AAoJEBx+YmzsjxAgh+YP/2Dap9JSDJEdFxyAGMvmtDag +BhgWZUZZiAWcJpfHL0sdFR6lvdi0QaMnRnOcBDQR6sfdiQ/GJaYy59/yLZQivf4B +nmWYeDSo6BabcXJXAdqClQ7bcg9yPToHRMjf5pGLt9B9CjVwue8Y+jaeW7AxSurO +HcgEPT8A3rOTNSoj5MTZTdKI/cspdcIKlKLrKPWDIDQt4vP2rVkVCYXfoqM0rvn+ +K/qVkilu+494LPxgvJu0ZDnuUxYQWs1sEc94cTRM/bTFC5luyT/PuByuXqz1BkN8 +H+3eO3rByAd4tpXC8Ku00iytUXpvIWppQIJe+USf7KuZINpeCs9g9fUjd40mX6/X +f/K/fisYMtKJ+6QWT+gIcacSfYWSpo4f9721DjaeSE//pvGZyotbW8t8AHqoXNOj +8bITKt1ZwMN1uM5hPh3s9rRPggmmwAPqe6cuS7V0gNfx6LtGAX+hTtpBfD1qhr0I +TUAdU4IT1VEz8iHfCe21Gu2WVsYZuEm+ernfzxgLaFAXBmIuLJscExIMxtc5TKzy +qzVZ1H9caIJQpUBvRuRSCoz2ZVUtshJIrSmJHXCaxwZjwW+RUU97xKZF/D6vksie +B9dmliNNJqTmZdoQpAZ4ewGwOQ+V6hKO4NK2UnNolt0vyn74uortFuHNO4DXW7Fg +PFJxECgVKV1Dy91MgJTA +=G1bW +-----END PGP SIGNATURE----- diff --git a/N2/2.hdr b/N2/2.hdr new file mode 100644 index 0000000..3237378 --- /dev/null +++ b/N2/2.hdr @@ -0,0 +1,2 @@ +Content-Type: application/pgp-signature; name="signature.asc" +Content-Description: Digital signature diff --git a/a/content_digest b/N2/content_digest index 10469a7..f9cca0c 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,27 +1,26 @@ "ref\01450445451-311-1-git-send-email-vishnupatekar0510@gmail.com\0" "ref\01450445451-311-3-git-send-email-vishnupatekar0510@gmail.com\0" - "ref\01450445451-311-3-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" - "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "From\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" "Subject\0Re: [PATCH v3 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi\0" "Date\0Fri, 18 Dec 2015 22:41:12 +0100\0" - "To\0Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" - corbet-T1hC0tSOHrs@public.gmane.org - pawel.moll-5wv7dgnIgG8@public.gmane.org - mark.rutland-5wv7dgnIgG8@public.gmane.org - ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org - galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org - emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org - linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org - hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org - wens-jdAy2FN1RRM@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org - " linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0Vishnu Patekar <vishnupatekar0510@gmail.com>\0" + "Cc\0robh+dt@kernel.org" + corbet@lwn.net + pawel.moll@arm.com + mark.rutland@arm.com + ijc+devicetree@hellion.org.uk + galak@codeaurora.org + linux@arm.linux.org.uk + emilio@elopez.com.ar + linus.walleij@linaro.org + jenskuske@gmail.com + hdegoede@redhat.com + wens@csie.org + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + linux-sunxi@googlegroups.com + " linux-gpio@vger.kernel.org\0" "\01:1\0" "b\0" "Hi,\n" @@ -31,7 +30,7 @@ "> This adds the basic dtsi, the clocks differs from\n" "> earlier sun8i SOCs.\n" "> \n" - "> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" + "> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\n" "> ---\n" "> arch/arm/boot/dts/sun8i-a83t.dtsi | 206 ++++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 206 insertions(+)\n" @@ -46,7 +45,7 @@ "> +/*\n" "> + * Copyright 2015 Vishnu Patekar\n" "> + *\n" - "> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" + "> + * Vishnu Patekar <vishnupatekar0510@gmail.com>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -272,5 +271,26 @@ "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" http://free-electrons.com + "\01:2\0" + "fn\0signature.asc\0" + "d\0Digital signature\0" + "b\0" + "-----BEGIN PGP SIGNATURE-----\n" + "Version: GnuPG v1\n" + "\n" + "iQIcBAEBAgAGBQJWdH14AAoJEBx+YmzsjxAgh+YP/2Dap9JSDJEdFxyAGMvmtDag\n" + "BhgWZUZZiAWcJpfHL0sdFR6lvdi0QaMnRnOcBDQR6sfdiQ/GJaYy59/yLZQivf4B\n" + "nmWYeDSo6BabcXJXAdqClQ7bcg9yPToHRMjf5pGLt9B9CjVwue8Y+jaeW7AxSurO\n" + "HcgEPT8A3rOTNSoj5MTZTdKI/cspdcIKlKLrKPWDIDQt4vP2rVkVCYXfoqM0rvn+\n" + "K/qVkilu+494LPxgvJu0ZDnuUxYQWs1sEc94cTRM/bTFC5luyT/PuByuXqz1BkN8\n" + "H+3eO3rByAd4tpXC8Ku00iytUXpvIWppQIJe+USf7KuZINpeCs9g9fUjd40mX6/X\n" + "f/K/fisYMtKJ+6QWT+gIcacSfYWSpo4f9721DjaeSE//pvGZyotbW8t8AHqoXNOj\n" + "8bITKt1ZwMN1uM5hPh3s9rRPggmmwAPqe6cuS7V0gNfx6LtGAX+hTtpBfD1qhr0I\n" + "TUAdU4IT1VEz8iHfCe21Gu2WVsYZuEm+ernfzxgLaFAXBmIuLJscExIMxtc5TKzy\n" + "qzVZ1H9caIJQpUBvRuRSCoz2ZVUtshJIrSmJHXCaxwZjwW+RUU97xKZF/D6vksie\n" + "B9dmliNNJqTmZdoQpAZ4ewGwOQ+V6hKO4NK2UnNolt0vyn74uortFuHNO4DXW7Fg\n" + "PFJxECgVKV1Dy91MgJTA\n" + "=G1bW\n" + "-----END PGP SIGNATURE-----\n" -b0e77dd479ce33a72c26ccc52d974a63b4e6119f8aeeb59082d8708c3ee7fcbe +8c999f19501b5c0697e845ec2e2e7bef408361e720f5e6d30e7dc12895670932
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