diff for duplicates of <201512212313.34114.arnd@arndb.de> diff --git a/a/1.txt b/N1/1.txt index cb535c4..ada3d65 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -9,10 +9,10 @@ On Monday 21 December 2015, Dr. Philipp Tomsich wrote: > > > > This would mean we cannot pass 64-bit arguments in registers, right? > -> Note that there?s no 32bit registers (the ?w?-form always refers to the lower -> 32bits of a 64bit register, with implicit zero-extension)? and load/store -> instructions always use the full base-register (?x?-form) for address calculation. -> I.e. a load/store would inadvertently pickup ?random garbage? in the upper +> Note that there’s no 32bit registers (the ‘w’-form always refers to the lower +> 32bits of a 64bit register, with implicit zero-extension)… and load/store +> instructions always use the full base-register (‘x’-form) for address calculation. +> I.e. a load/store would inadvertently pickup “random garbage” in the upper > 32bits, if no explicit zero-extension is applied. > > In other words: all zero-extensions for 32bit arguments should be explicit diff --git a/a/content_digest b/N1/content_digest index 55fab46..82a9abe 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,29 @@ "ref\01450215766-14765-1-git-send-email-ynorov@caviumnetworks.com\0" "ref\02334903.IjsQ1BK3JF@wuerfel\0" "ref\04753CD2F-914D-44D5-BD18-8DF94068315D@theobroma-systems.com\0" - "From\0arnd@arndb.de (Arnd Bergmann)\0" - "Subject\0[PATCH v6 12/20] arm64:ilp32: add sys_ilp32.c and a separate table (in entry.S) to use it\0" + "From\0Arnd Bergmann <arnd@arndb.de>\0" + "Subject\0Re: [PATCH v6 12/20] arm64:ilp32: add sys_ilp32.c and a separate table (in entry.S) to use it\0" "Date\0Mon, 21 Dec 2015 23:13:33 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Dr. Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\0" + "Cc\0Catalin Marinas <catalin.marinas@arm.com>" + Andrew Pinski <pinskia@gmail.com> + Joseph S. Myers <joseph@codesourcery.com> + Kapoor + Prasun <Prasun.Kapoor@caviumnetworks.com> + broonie@kernel.org + Nathan Lynch <Nathan_Lynch@mentor.com> + LKML <linux-kernel@vger.kernel.org> + Alexander Graf <agraf@suse.de> + Alexey Klimov <klimov.linux@gmail.com> + Yury Norov <ynorov@caviumnetworks.com> + Jan Dakinevich <jan.dakinevich@gmail.com> + Andrew Pinski <apinski@cavium.com> + David Daney <ddaney.cavm@gmail.com> + Andreas Schwab <schwab@suse.de> + Zhangjian (Bamvor) <bamvor.zhangjian@huawei.com> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + " Christoph M\303\274llner <christoph.muellner@theobroma-systems.com>" + " Marcus Shawcroft <Marcus.Shawcroft@arm.com>\0" "\00:1\0" "b\0" "On Monday 21 December 2015, Dr. Philipp Tomsich wrote:\n" @@ -18,10 +37,10 @@ "> > \n" "> > This would mean we cannot pass 64-bit arguments in registers, right?\n" "> \n" - "> Note that there?s no 32bit registers (the ?w?-form always refers to the lower\n" - "> 32bits of a 64bit register, with implicit zero-extension)? and load/store\n" - "> instructions always use the full base-register (?x?-form) for address calculation.\n" - "> I.e. a load/store would inadvertently pickup ?random garbage? in the upper \n" + "> Note that there\342\200\231s no 32bit registers (the \342\200\230w\342\200\231-form always refers to the lower\n" + "> 32bits of a 64bit register, with implicit zero-extension)\342\200\246 and load/store\n" + "> instructions always use the full base-register (\342\200\230x\342\200\231-form) for address calculation.\n" + "> I.e. a load/store would inadvertently pickup \342\200\234random garbage\342\200\235 in the upper \n" "> 32bits, if no explicit zero-extension is applied.\n" "> \n" "> In other words: all zero-extensions for 32bit arguments should be explicit\n" @@ -36,4 +55,4 @@ "\n" "\tArnd" -41186d121ad3a5a98460986a612a3c279fca9f1fd13923181be0dd66e72b4aab +ab5d157733dd9b8cdb01216ea94f3c91d47da2ffb6a57744eb9fcfc918e8d279
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