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From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [linux-sunxi] Re: PSCI for H3
Date: Wed, 23 Dec 2015 12:14:15 +0200	[thread overview]
Message-ID: <20151223121415.050a3955@i7> (raw)
In-Reply-To: <564B3A7E.6040800@gmail.com>

On Tue, 17 Nov 2015 15:32:30 +0100
Jens Kuske <jenskuske@gmail.com> wrote:

> On 16/11/15 07:26, Chen-Yu Tsai wrote:
> > Hi everyone,
> > 
> > I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that
> > includes Jens' patches.
> > 
> > For PSCI and SMP, it seems the H3 follows the structure of previous sun8i SoCs.
> > The CPUCFG registers line up. The manual doesn't have the PRCM, so I'll have to
> > dig through the SDK.
> > 
> > One other thing is the SMTA, or Secure Memory Touch Arbiter, which we last
> > encountered issues with on the A31s. This controls non-secure access to a whole
> > bunch of peripherals, which we'll need to enable for Linux to run non-secure.  
> 
> There is also register 0x2f0 in the CCU, it defaults to disabling
> non-secure access to all clock registers.
> 
> Jens
> 

How about just enabling SMP on Allwinner H3 in an old unfashionable way
while all these non-secure access limiters are still being under
investigation?



diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 0faa38a..d23ed84 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -51,6 +51,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "allwinner,sun6i-a31";
 
 		cpu at 0 {
 			compatible = "arm,cortex-a7";
@@ -591,5 +592,15 @@
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		prcm at 01f01400 {
+			compatible = "allwinner,sun8i-h3-prcm";
+			reg = <0x01f01400 0x200>;
+		};
+
+		cpucfg at 01f01c00 {
+			compatible = "allwinner,sun8i-h3-cpuconfig";
+			reg = <0x01f01c00 0x300>;
+		};
 	};
 };
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index e8483ec..8ca4064 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -44,6 +44,9 @@ static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
 	struct device_node *node;
 
 	node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
+	if (!node)
+		node = of_find_compatible_node(NULL, NULL,
+					       "allwinner,sun8i-h3-prcm");
 	if (!node) {
 		pr_err("Missing A31 PRCM node in the device tree\n");
 		return;
@@ -57,6 +60,9 @@ static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
 
 	node = of_find_compatible_node(NULL, NULL,
 				       "allwinner,sun6i-a31-cpuconfig");
+	if (!node)
+		node = of_find_compatible_node(NULL, NULL,
+					       "allwinner,sun8i-h3-cpuconfig");
 	if (!node) {
 		pr_err("Missing A31 CPU config node in the device tree\n");
 		return;
-- 
2.4.10


-- 
Best regards,
Siarhei Siamashka

  reply	other threads:[~2015-12-23 10:14 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-16  6:24 [U-Boot] PSCI for H3 wens Tsai
2015-11-16  6:26 ` [U-Boot] Fwd: " Chen-Yu Tsai
2015-11-17 14:32   ` [U-Boot] " Jens Kuske
2015-12-23 10:14     ` Siarhei Siamashka [this message]
2015-12-23 14:36       ` [U-Boot] [linux-sunxi] " Chen-Yu Tsai
2015-12-23 14:56         ` Siarhei Siamashka
2015-12-27 17:16       ` Maxime Ripard
2016-01-04  4:02         ` Chen-Yu Tsai

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