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From: Alexander Duyck <aduyck@mirantis.com>
To: intel-wired-lan@osuosl.org
Subject: [Intel-wired-lan] [next PATCH 01/11] igb: clean up code for setting MAC address
Date: Wed, 06 Jan 2016 23:10:23 -0800	[thread overview]
Message-ID: <20160107071023.13648.94040.stgit@localhost.localdomain> (raw)
In-Reply-To: <20160107070850.13648.21033.stgit@localhost.localdomain>

Drop a bunch of hand written byte swapping code in favor of just doing the
byte swapping ourselves.  The registers are little endian registers storing
a big endian value so if we read the MAC address array as little endian
then we will get the CPU registers into the proper layout.

Signed-off-by: Alexander Duyck <aduyck@mirantis.com>
---
 drivers/net/ethernet/intel/igb/igb_main.c |    9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index 637135e216e4..3b6d4e10d095 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -7834,15 +7834,14 @@ static void igb_io_resume(struct pci_dev *pdev)
 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
 			     u8 qsel)
 {
-	u32 rar_low, rar_high;
 	struct e1000_hw *hw = &adapter->hw;
+	u32 rar_low, rar_high;
 
 	/* HW expects these in little endian so we reverse the byte order
-	 * from network order (big endian) to little endian
+	 * from network order (big endian) to CPU endian
 	 */
-	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
-		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
-	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
+	rar_low = le32_to_cpup((__be32 *)(addr));
+	rar_high = le16_to_cpup((__be16 *)(addr + 4));
 
 	/* Indicate to hardware the Address is Valid. */
 	rar_high |= E1000_RAH_AV;


  reply	other threads:[~2016-01-07  7:10 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-07  7:10 [Intel-wired-lan] [next PATCH 00/11] Enable use of PF for switch or bridge when using SR-IOV Alexander Duyck
2016-01-07  7:10 ` Alexander Duyck [this message]
2016-01-14  3:06   ` [Intel-wired-lan] [next PATCH 01/11] igb: clean up code for setting MAC address Brown, Aaron F
2016-01-07  7:10 ` [Intel-wired-lan] [next PATCH 02/11] igb: Refactor VFTA configuration Alexander Duyck
2016-01-14  3:09   ` Brown, Aaron F
2016-01-07  7:10 ` [Intel-wired-lan] [next PATCH 03/11] igb: Allow asymmetric configuration of MTU versus Rx frame size Alexander Duyck
2016-01-12 18:03   ` Hisashi T Fujinaka
2016-01-12 21:34     ` Alexander Duyck
2016-01-12 23:13       ` Hisashi T Fujinaka
2016-01-14  3:07   ` Brown, Aaron F
2016-01-07  7:10 ` [Intel-wired-lan] [next PATCH 04/11] igb: Do not factor VLANs into RLPML calculation Alexander Duyck
2016-01-14  3:10   ` Brown, Aaron F
2016-01-07  7:10 ` [Intel-wired-lan] [next PATCH 05/11] igb: Always enable VLAN 0 even if 8021q is not loaded Alexander Duyck
2016-01-14  3:11   ` Brown, Aaron F
2016-01-07  7:11 ` [Intel-wired-lan] [next PATCH 06/11] igb: Merge VLVF configuration into igb_vfta_set Alexander Duyck
2016-01-14  3:12   ` Brown, Aaron F
2016-01-07  7:11 ` [Intel-wired-lan] [next PATCH 07/11] igb: Clean-up configuration of VF port VLANs Alexander Duyck
2016-01-14  3:13   ` Brown, Aaron F
2016-01-07  7:11 ` [Intel-wired-lan] [next PATCH 08/11] igb: Add support for VLAN promiscuous with SR-IOV and NTUPLE Alexander Duyck
2016-01-14  3:14   ` Brown, Aaron F
2016-01-07  7:11 ` [Intel-wired-lan] [next PATCH 09/11] igb: Drop unnecessary checks in transmit path Alexander Duyck
2016-01-14  3:15   ` Brown, Aaron F
2016-01-07  7:11 ` [Intel-wired-lan] [next PATCH 10/11] igb: Enable use of "bridge fdb add" to set unicast table entries Alexander Duyck
2016-01-14  3:16   ` Brown, Aaron F
2016-01-07  7:11 ` [Intel-wired-lan] [next PATCH 11/11] igb: Add workaround for VLAN tag stripping on 82576 Alexander Duyck
2016-01-14  3:17   ` Brown, Aaron F

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