Re: [Qemu-devel] [PATCH v2] target-mips: Fix ALIGN instruction when bp=0

[Aurelien Jarno <aurelien@aurel32.net>]

> From e48787a25de9a04985226cd7651795403d5752e6 Mon Sep 17 00:00:00 2001
> From: Miodrag Dinic <miodrag.dinic@imgtec.com>
> Date: Thu, 3 Dec 2015 16:48:57 +0100
> Subject: [PATCH] [PATCH v2] target-mips: Fix ALIGN instruction when bp=0
> 
> If executing ALIGN with shift count bp=0 within mips64 emulation,
> the result of the operation should be sign extended.
> 
> Taken from the official documentation (pseudo code) :
> 
> ALIGN:
> 	tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp)
> 	tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp))
> 	tmp = tmp_rt_hi || tmp_rt_lo
> 	GPR[rd] = sign_extend.32(tmp)
> 
> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
> ---
>  target-mips/translate.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 5626647..d2443d3 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -4630,7 +4630,16 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
>      t0 = tcg_temp_new();
>      gen_load_gpr(t0, rt);
>      if (bp == 0) {
> -        tcg_gen_mov_tl(cpu_gpr[rd], t0);
> +        switch (opc) {
> +        case OPC_ALIGN:
> +            tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
> +            break;
> +#if defined(TARGET_MIPS64)
> +        case OPC_DALIGN:
> +            tcg_gen_mov_tl(cpu_gpr[rd], t0);
> +            break;
> +#endif
> +        }
>      } else {
>          TCGv t1 = tcg_temp_new();
>          gen_load_gpr(t1, rs);

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net