From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoffer Dall Subject: Re: [PATCH v8 20/20] KVM: ARM64: Add a new kvm ARM PMU device Date: Sat, 9 Jan 2016 13:29:56 +0100 Message-ID: <20160109122956.GA30867@cbox> References: <1450771695-11948-1-git-send-email-zhaoshenglong@huawei.com> <1450771695-11948-21-git-send-email-zhaoshenglong@huawei.com> <568E7AF1.9040103@huawei.com> <20160107203647.GJ6199@hawk.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 646894993D for ; Sat, 9 Jan 2016 07:25:31 -0500 (EST) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kH7hQyM-yust for ; Sat, 9 Jan 2016 07:25:30 -0500 (EST) Received: from mail-wm0-f46.google.com (mail-wm0-f46.google.com [74.125.82.46]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 6605B497F8 for ; Sat, 9 Jan 2016 07:25:30 -0500 (EST) Received: by mail-wm0-f46.google.com with SMTP id f206so206980050wmf.0 for ; Sat, 09 Jan 2016 04:29:21 -0800 (PST) Content-Disposition: inline In-Reply-To: <20160107203647.GJ6199@hawk.localdomain> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Andrew Jones Cc: kvm-devel , Marc Zyngier , Will Deacon , Shannon Zhao , "kvmarm@lists.cs.columbia.edu" , arm-mail-list List-Id: kvmarm@lists.cs.columbia.edu On Thu, Jan 07, 2016 at 09:36:47PM +0100, Andrew Jones wrote: > On Thu, Jan 07, 2016 at 02:56:15PM +0000, Peter Maydell wrote: > > On 7 January 2016 at 14:49, Shannon Zhao wrote: > > >>> + > > >>> +Groups: > > >>> + KVM_DEV_ARM_PMU_GRP_IRQ > > >>> + Attributes: > > >>> + The attr field of kvm_device_attr encodes one value: > > >>> + bits: | 63 .... 32 | 31 .... 0 | > > >>> + values: | reserved | vcpu_index | > > >>> + A value describing the PMU overflow interrupt number for the specified > > >>> + vcpu_index vcpu. This interrupt could be a PPI or SPI, but for one VM the > > >>> + interrupt type must be same for each vcpu. As a PPI, the interrupt number is > > >>> + same for all vcpus, while as a SPI it must be different for each vcpu. > > >> > > >> I see we're using vcpu_index rather than MPIDR affinity value > > >> for specifying which CPU we're configuring. Is this in line with > > >> our planned API for GICv3 configuration? > > >> > > > Here vcpu_index is used to indexing the vCPU, no special use. > > > > Yes, but you can identify the CPU by index, or by its MPIDR. > > We had a discussion about which was the best way for doing > > the VGIC API, and I can't remember which way round we ended up > > going for. Whichever we chose, we should do the same thing here. > > I think we should start up a new discussion on this. My understanding, > after a chat with Igor, who was involved in the untangling of vcpu-id and > apic-id for x86, is that using vcpu-id is preferred, unless of course > the device expects an apic-id/mpidr, in which case there's no reason to > translate it on both sides. > I'm fairly strongly convinced that we should use the full 32-bit compressed MPIDR for everything ARM related going forward, as this will cover any case required and leverages and architecturally defined way of uniquely identifying a (v)CPU. -Christoffer From mboxrd@z Thu Jan 1 00:00:00 1970 From: christoffer.dall@linaro.org (Christoffer Dall) Date: Sat, 9 Jan 2016 13:29:56 +0100 Subject: [PATCH v8 20/20] KVM: ARM64: Add a new kvm ARM PMU device In-Reply-To: <20160107203647.GJ6199@hawk.localdomain> References: <1450771695-11948-1-git-send-email-zhaoshenglong@huawei.com> <1450771695-11948-21-git-send-email-zhaoshenglong@huawei.com> <568E7AF1.9040103@huawei.com> <20160107203647.GJ6199@hawk.localdomain> Message-ID: <20160109122956.GA30867@cbox> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Jan 07, 2016 at 09:36:47PM +0100, Andrew Jones wrote: > On Thu, Jan 07, 2016 at 02:56:15PM +0000, Peter Maydell wrote: > > On 7 January 2016 at 14:49, Shannon Zhao wrote: > > >>> + > > >>> +Groups: > > >>> + KVM_DEV_ARM_PMU_GRP_IRQ > > >>> + Attributes: > > >>> + The attr field of kvm_device_attr encodes one value: > > >>> + bits: | 63 .... 32 | 31 .... 0 | > > >>> + values: | reserved | vcpu_index | > > >>> + A value describing the PMU overflow interrupt number for the specified > > >>> + vcpu_index vcpu. This interrupt could be a PPI or SPI, but for one VM the > > >>> + interrupt type must be same for each vcpu. As a PPI, the interrupt number is > > >>> + same for all vcpus, while as a SPI it must be different for each vcpu. > > >> > > >> I see we're using vcpu_index rather than MPIDR affinity value > > >> for specifying which CPU we're configuring. Is this in line with > > >> our planned API for GICv3 configuration? > > >> > > > Here vcpu_index is used to indexing the vCPU, no special use. > > > > Yes, but you can identify the CPU by index, or by its MPIDR. > > We had a discussion about which was the best way for doing > > the VGIC API, and I can't remember which way round we ended up > > going for. Whichever we chose, we should do the same thing here. > > I think we should start up a new discussion on this. My understanding, > after a chat with Igor, who was involved in the untangling of vcpu-id and > apic-id for x86, is that using vcpu-id is preferred, unless of course > the device expects an apic-id/mpidr, in which case there's no reason to > translate it on both sides. > I'm fairly strongly convinced that we should use the full 32-bit compressed MPIDR for everything ARM related going forward, as this will cover any case required and leverages and architecturally defined way of uniquely identifying a (v)CPU. -Christoffer