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Date: Thu, 14 Jan 2016 11:29:48 -0500
From: Kevin O'Connor <kevin@koconnor.net>
Message-ID: <20160114162948.GA1901@morn.lan>
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Subject: Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU
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To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: valentine.sinitsyn@gmail.com, qemu-devel@nongnu.org, crosthwaitepeter@gmail.com, jan.kiszka@web.de, marcel@redhat.com, David Kiarie <davidkiarie4@gmail.com>

On Thu, Jan 14, 2016 at 12:09:46PM +0200, Michael S. Tsirkin wrote:
> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
> > Add IVRS table for AMD IO MMU. Also reverve MMIO
> 
> reserve?
> 
> > region for IO MMU via ACPI
> 
> 
> It does not look like you reserve anything.
> 
> Pls add a link to hardware spec (in
> the device implementation) so we can check
> what does real hardware do.
> 
> If this is it:
> http://developer.amd.com/wordpress/media/2012/10/488821.pdf
> 
> then the way that works seems to be by guest
> programming the MMIO base.
> We should do the same: patch seabios and EFI to do this.

A similar question - how does a typical factory BIOS select which
address to set as the MMIO base?  Is it generally hard-coded or is it
allocated from a range in some way?

-Kevin