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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id j3sm2818365wmj.19.2016.01.15.06.38.44 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 15 Jan 2016 06:38:45 -0800 (PST) Date: Fri, 15 Jan 2016 15:38:36 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org, qemu-arm@nongnu.org, Paolo Bonzini , Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() Message-ID: <20160115143836.GI29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-2-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452796451-2946-2-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TUID: 1pbJl0EmtNg6 On Thu, Jan 14, 2016 at 06:34:04PM +0000, Peter Maydell wrote: > Support EL2 and EL3 in arm_el_is_aa64() by implementing the > logic for checking the SCR_EL3 and HCR_EL2 register-width bits > as appropriate to determine the register width of lower exception > levels. > > Signed-off-by: Peter Maydell Hi Peter, On the ZynqMP we've got the Cortex-A53 EL3 RW configurable at reset time. At some later point we'll likely have to implement that runtime option... Anyway: Reviewed-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 33 ++++++++++++++++++++++++--------- > 1 file changed, 24 insertions(+), 9 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 5f81342..b8b3364 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -969,18 +969,33 @@ static inline bool arm_is_secure(CPUARMState *env) > /* Return true if the specified exception level is running in AArch64 state. */ > static inline bool arm_el_is_aa64(CPUARMState *env, int el) > { > - /* We don't currently support EL2, and this isn't valid for EL0 > - * (if we're in EL0, is_a64() is what you want, and if we're not in EL0 > - * then the state of EL0 isn't well defined.) > + /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, > + * and if we're not in EL0 then the state of EL0 isn't well defined.) > */ > - assert(el == 1 || el == 3); > + assert(el >= 1 && el <= 3); > + bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); > > - /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This > - * is a QEMU-imposed simplification which we may wish to change later. > - * If we in future support EL2 and/or EL3, then the state of lower > - * exception levels is controlled by the HCR.RW and SCR.RW bits. > + /* The highest exception level is always at the maximum supported > + * register width, and then lower levels have a register width controlled > + * by bits in the SCR or HCR registers. > */ > - return arm_feature(env, ARM_FEATURE_AARCH64); > + if (el == 3) { > + return aa64; > + } > + > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); > + } > + > + if (el == 2) { > + return aa64; > + } > + > + if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { > + aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); > + } > + > + return aa64; > } > > /* Function for determing whether guest cp register reads and writes should > -- > 1.9.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36090) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aK5Wa-0003uw-9f for qemu-devel@nongnu.org; Fri, 15 Jan 2016 09:38:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aK5WZ-0004Tg-7d for qemu-devel@nongnu.org; Fri, 15 Jan 2016 09:38:48 -0500 Date: Fri, 15 Jan 2016 15:38:36 +0100 From: "Edgar E. Iglesias" Message-ID: <20160115143836.GI29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-2-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452796451-2946-2-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , qemu-arm@nongnu.org, Alex =?iso-8859-1?Q?Benn=E9e?= , qemu-devel@nongnu.org, patches@linaro.org On Thu, Jan 14, 2016 at 06:34:04PM +0000, Peter Maydell wrote: > Support EL2 and EL3 in arm_el_is_aa64() by implementing the > logic for checking the SCR_EL3 and HCR_EL2 register-width bits > as appropriate to determine the register width of lower exception > levels. > > Signed-off-by: Peter Maydell Hi Peter, On the ZynqMP we've got the Cortex-A53 EL3 RW configurable at reset time. At some later point we'll likely have to implement that runtime option... Anyway: Reviewed-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 33 ++++++++++++++++++++++++--------- > 1 file changed, 24 insertions(+), 9 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 5f81342..b8b3364 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -969,18 +969,33 @@ static inline bool arm_is_secure(CPUARMState *env) > /* Return true if the specified exception level is running in AArch64 state. */ > static inline bool arm_el_is_aa64(CPUARMState *env, int el) > { > - /* We don't currently support EL2, and this isn't valid for EL0 > - * (if we're in EL0, is_a64() is what you want, and if we're not in EL0 > - * then the state of EL0 isn't well defined.) > + /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, > + * and if we're not in EL0 then the state of EL0 isn't well defined.) > */ > - assert(el == 1 || el == 3); > + assert(el >= 1 && el <= 3); > + bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); > > - /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This > - * is a QEMU-imposed simplification which we may wish to change later. > - * If we in future support EL2 and/or EL3, then the state of lower > - * exception levels is controlled by the HCR.RW and SCR.RW bits. > + /* The highest exception level is always at the maximum supported > + * register width, and then lower levels have a register width controlled > + * by bits in the SCR or HCR registers. > */ > - return arm_feature(env, ARM_FEATURE_AARCH64); > + if (el == 3) { > + return aa64; > + } > + > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); > + } > + > + if (el == 2) { > + return aa64; > + } > + > + if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { > + aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); > + } > + > + return aa64; > } > > /* Function for determing whether guest cp register reads and writes should > -- > 1.9.1 >