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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id l3sm15589054oeq.0.2016.01.19.08.40.19 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 19 Jan 2016 08:40:24 -0800 (PST) Date: Tue, 19 Jan 2016 17:40:16 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org, qemu-arm@nongnu.org, Paolo Bonzini , Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH 5/8] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target Message-ID: <20160119164016.GO29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-6-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452796451-2946-6-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TUID: vy6CeUjRlJUy On Thu, Jan 14, 2016 at 06:34:08PM +0000, Peter Maydell wrote: > The entry offset when taking an exception to AArch64 from a lower > exception level may be 0x400 or 0x600. 0x400 is used if the > implemented exception level immediately lower than the target level > is using AArch64, and 0x600 if it is using AArch32. We were > incorrectly implementing this as checking the exception level > that the exception was taken from. (The two can be different if > for example we take an exception from EL0 to AArch64 EL3; we should > in this case be checking EL2 if EL2 is implemented, and EL1 if > EL2 is not implemented.) > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 21 ++++++++++++++++++++- > 1 file changed, 20 insertions(+), 1 deletion(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index d37c82c..196c111 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -5866,7 +5866,26 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) > unsigned int new_mode = aarch64_pstate_mode(new_el, true); > > if (arm_current_el(env) < new_el) { > - if (env->aarch64) { > + /* Entry vector offset depends on whether the implemented EL > + * immediately lower than the target level is using AArch32 or AArch64 > + */ > + bool is_aa64; > + > + switch (new_el) { > + case 3: > + is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; > + break; > + case 2: > + is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; > + break; > + case 1: > + is_aa64 = is_a64(env); > + break; > + default: > + g_assert_not_reached(); > + } > + > + if (is_aa64) { > addr += 0x400; > } else { > addr += 0x600; > -- > 1.9.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52747) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLZKY-00067C-8P for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:40:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLZKU-0002Fv-TU for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:40:30 -0500 Date: Tue, 19 Jan 2016 17:40:16 +0100 From: "Edgar E. Iglesias" Message-ID: <20160119164016.GO29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-6-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452796451-2946-6-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 5/8] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , qemu-arm@nongnu.org, Alex =?iso-8859-1?Q?Benn=E9e?= , qemu-devel@nongnu.org, patches@linaro.org On Thu, Jan 14, 2016 at 06:34:08PM +0000, Peter Maydell wrote: > The entry offset when taking an exception to AArch64 from a lower > exception level may be 0x400 or 0x600. 0x400 is used if the > implemented exception level immediately lower than the target level > is using AArch64, and 0x600 if it is using AArch32. We were > incorrectly implementing this as checking the exception level > that the exception was taken from. (The two can be different if > for example we take an exception from EL0 to AArch64 EL3; we should > in this case be checking EL2 if EL2 is implemented, and EL1 if > EL2 is not implemented.) > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 21 ++++++++++++++++++++- > 1 file changed, 20 insertions(+), 1 deletion(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index d37c82c..196c111 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -5866,7 +5866,26 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) > unsigned int new_mode = aarch64_pstate_mode(new_el, true); > > if (arm_current_el(env) < new_el) { > - if (env->aarch64) { > + /* Entry vector offset depends on whether the implemented EL > + * immediately lower than the target level is using AArch32 or AArch64 > + */ > + bool is_aa64; > + > + switch (new_el) { > + case 3: > + is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; > + break; > + case 2: > + is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; > + break; > + case 1: > + is_aa64 = is_a64(env); > + break; > + default: > + g_assert_not_reached(); > + } > + > + if (is_aa64) { > addr += 0x400; > } else { > addr += 0x600; > -- > 1.9.1 >