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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id w6sm15875086obx.9.2016.01.19.08.47.55 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 19 Jan 2016 08:47:56 -0800 (PST) Date: Tue, 19 Jan 2016 17:47:52 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org, qemu-arm@nongnu.org, Paolo Bonzini , Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH 6/8] target-arm: Handle exception return from AArch64 to non-EL0 AArch32 Message-ID: <20160119164752.GP29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-7-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452796451-2946-7-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TUID: pQsztPVljl+/ On Thu, Jan 14, 2016 at 06:34:09PM +0000, Peter Maydell wrote: > Remove the assumptions that the AArch64 exception return code was > making about a return to AArch32 always being a return to EL0. > This includes pulling out the illegal-SPSR checks so we can apply > them for return to 32 bit as well as return to 64-bit. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/op_helper.c | 80 +++++++++++++++++++++++++++++++++++++------------- > 1 file changed, 59 insertions(+), 21 deletions(-) > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index e42d287..38d46d8 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -640,12 +640,51 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) > } > } > > +static int el_from_spsr(uint32_t spsr) > +{ > + /* Return the exception level that this SPSR is requesting a return to, > + * or -1 if it is invalid (an illegal return) > + */ > + if (spsr & PSTATE_nRW) { > + switch (spsr & CPSR_M) { > + case ARM_CPU_MODE_USR: > + return 0; > + case ARM_CPU_MODE_HYP: > + return 2; > + case ARM_CPU_MODE_FIQ: > + case ARM_CPU_MODE_IRQ: > + case ARM_CPU_MODE_SVC: > + case ARM_CPU_MODE_ABT: > + case ARM_CPU_MODE_UND: > + case ARM_CPU_MODE_SYS: > + return 1; > + case ARM_CPU_MODE_MON: > + /* Returning to Mon from AArch64 is never possible, > + * so this is an illegal return. > + */ > + default: > + return -1; > + } > + } else { > + if (extract32(spsr, 1, 1)) { > + /* Return with reserved M[1] bit set */ > + return -1; > + } > + if (extract32(spsr, 0, 4) == 1) { > + /* return to EL0 with M[0] bit set */ > + return -1; > + } > + return extract32(spsr, 2, 2); > + } > +} > + > void HELPER(exception_return)(CPUARMState *env) > { > int cur_el = arm_current_el(env); > unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); > uint32_t spsr = env->banked_spsr[spsr_idx]; > int new_el; > + bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; > > aarch64_save_sp(env, cur_el); > > @@ -662,35 +701,34 @@ void HELPER(exception_return)(CPUARMState *env) > spsr &= ~PSTATE_SS; > } > > - if (spsr & PSTATE_nRW) { > - /* TODO: We currently assume EL1/2/3 are running in AArch64. */ > + new_el = el_from_spsr(spsr); > + if (new_el == -1) { > + goto illegal_return; > + } > + if (new_el > cur_el > + || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { > + /* Disallow return to an EL which is unimplemented or higher > + * than the current one. > + */ > + goto illegal_return; > + } > + > + if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { > + /* Return to an EL which is configured for a different register width */ > + goto illegal_return; > + } > + > + if (!return_to_aa64) { > env->aarch64 = 0; > - new_el = 0; > - env->uncached_cpsr = 0x10; > + env->uncached_cpsr = spsr & CPSR_M; > cpsr_write(env, spsr, ~0); > if (!arm_singlestep_active(env)) { > env->uncached_cpsr &= ~PSTATE_SS; > } > aarch64_sync_64_to_32(env); > > - env->regs[15] = env->elr_el[1] & ~0x1; > + env->regs[15] = env->elr_el[cur_el] & ~0x1; > } else { > - new_el = extract32(spsr, 2, 2); > - if (new_el > cur_el > - || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { > - /* Disallow return to an EL which is unimplemented or higher > - * than the current one. > - */ > - goto illegal_return; > - } > - if (extract32(spsr, 1, 1)) { > - /* Return with reserved M[1] bit set */ > - goto illegal_return; > - } > - if (new_el == 0 && (spsr & PSTATE_SP)) { > - /* Return to EL0 with M[0] bit set */ > - goto illegal_return; > - } > env->aarch64 = 1; > pstate_write(env, spsr); > if (!arm_singlestep_active(env)) { > -- > 1.9.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56345) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLZRo-0005kC-CA for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:48:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLZRl-00051D-Me for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:48:00 -0500 Date: Tue, 19 Jan 2016 17:47:52 +0100 From: "Edgar E. Iglesias" Message-ID: <20160119164752.GP29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-7-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452796451-2946-7-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 6/8] target-arm: Handle exception return from AArch64 to non-EL0 AArch32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , qemu-arm@nongnu.org, Alex =?iso-8859-1?Q?Benn=E9e?= , qemu-devel@nongnu.org, patches@linaro.org On Thu, Jan 14, 2016 at 06:34:09PM +0000, Peter Maydell wrote: > Remove the assumptions that the AArch64 exception return code was > making about a return to AArch32 always being a return to EL0. > This includes pulling out the illegal-SPSR checks so we can apply > them for return to 32 bit as well as return to 64-bit. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/op_helper.c | 80 +++++++++++++++++++++++++++++++++++++------------- > 1 file changed, 59 insertions(+), 21 deletions(-) > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index e42d287..38d46d8 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -640,12 +640,51 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) > } > } > > +static int el_from_spsr(uint32_t spsr) > +{ > + /* Return the exception level that this SPSR is requesting a return to, > + * or -1 if it is invalid (an illegal return) > + */ > + if (spsr & PSTATE_nRW) { > + switch (spsr & CPSR_M) { > + case ARM_CPU_MODE_USR: > + return 0; > + case ARM_CPU_MODE_HYP: > + return 2; > + case ARM_CPU_MODE_FIQ: > + case ARM_CPU_MODE_IRQ: > + case ARM_CPU_MODE_SVC: > + case ARM_CPU_MODE_ABT: > + case ARM_CPU_MODE_UND: > + case ARM_CPU_MODE_SYS: > + return 1; > + case ARM_CPU_MODE_MON: > + /* Returning to Mon from AArch64 is never possible, > + * so this is an illegal return. > + */ > + default: > + return -1; > + } > + } else { > + if (extract32(spsr, 1, 1)) { > + /* Return with reserved M[1] bit set */ > + return -1; > + } > + if (extract32(spsr, 0, 4) == 1) { > + /* return to EL0 with M[0] bit set */ > + return -1; > + } > + return extract32(spsr, 2, 2); > + } > +} > + > void HELPER(exception_return)(CPUARMState *env) > { > int cur_el = arm_current_el(env); > unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); > uint32_t spsr = env->banked_spsr[spsr_idx]; > int new_el; > + bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; > > aarch64_save_sp(env, cur_el); > > @@ -662,35 +701,34 @@ void HELPER(exception_return)(CPUARMState *env) > spsr &= ~PSTATE_SS; > } > > - if (spsr & PSTATE_nRW) { > - /* TODO: We currently assume EL1/2/3 are running in AArch64. */ > + new_el = el_from_spsr(spsr); > + if (new_el == -1) { > + goto illegal_return; > + } > + if (new_el > cur_el > + || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { > + /* Disallow return to an EL which is unimplemented or higher > + * than the current one. > + */ > + goto illegal_return; > + } > + > + if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { > + /* Return to an EL which is configured for a different register width */ > + goto illegal_return; > + } > + > + if (!return_to_aa64) { > env->aarch64 = 0; > - new_el = 0; > - env->uncached_cpsr = 0x10; > + env->uncached_cpsr = spsr & CPSR_M; > cpsr_write(env, spsr, ~0); > if (!arm_singlestep_active(env)) { > env->uncached_cpsr &= ~PSTATE_SS; > } > aarch64_sync_64_to_32(env); > > - env->regs[15] = env->elr_el[1] & ~0x1; > + env->regs[15] = env->elr_el[cur_el] & ~0x1; > } else { > - new_el = extract32(spsr, 2, 2); > - if (new_el > cur_el > - || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { > - /* Disallow return to an EL which is unimplemented or higher > - * than the current one. > - */ > - goto illegal_return; > - } > - if (extract32(spsr, 1, 1)) { > - /* Return with reserved M[1] bit set */ > - goto illegal_return; > - } > - if (new_el == 0 && (spsr & PSTATE_SP)) { > - /* Return to EL0 with M[0] bit set */ > - goto illegal_return; > - } > env->aarch64 = 1; > pstate_write(env, spsr); > if (!arm_singlestep_active(env)) { > -- > 1.9.1 >