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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id sd7sm15481593oec.13.2016.01.19.08.56.34 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 19 Jan 2016 08:56:35 -0800 (PST) Date: Tue, 19 Jan 2016 17:56:31 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org, qemu-arm@nongnu.org, Paolo Bonzini , Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH 8/8] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode Message-ID: <20160119165631.GR29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-9-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452796451-2946-9-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TUID: skjAh+nu+V27 On Thu, Jan 14, 2016 at 06:34:11PM +0000, Peter Maydell wrote: > The architecture requires that for an exception return to AArch32 the > low bits of ELR_ELx are ignored when the PC is set from them: > * if returning to Thumb mode, ignore ELR_ELx[0] > * if returning to ARM mode, ignore ELR_ELx[1:0] > > We were only squashing bit 0; also squash bit 1 if the SPSR T bit > indicates this is a return to ARM code. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/op_helper.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 5789ccb..171d6b8 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -738,7 +738,11 @@ void HELPER(exception_return)(CPUARMState *env) > } > aarch64_sync_64_to_32(env); > > - env->regs[15] = env->elr_el[cur_el] & ~0x1; > + if (spsr & CPSR_T) { > + env->regs[15] = env->elr_el[cur_el] & ~0x1; > + } else { > + env->regs[15] = env->elr_el[cur_el] & ~0x3; > + } > } else { > env->aarch64 = 1; > pstate_write(env, spsr); > -- > 1.9.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLZaD-0008V7-GI for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:56:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLZa9-0007OW-B9 for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:56:41 -0500 Date: Tue, 19 Jan 2016 17:56:31 +0100 From: "Edgar E. Iglesias" Message-ID: <20160119165631.GR29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-9-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452796451-2946-9-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 8/8] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , qemu-arm@nongnu.org, Alex =?iso-8859-1?Q?Benn=E9e?= , qemu-devel@nongnu.org, patches@linaro.org On Thu, Jan 14, 2016 at 06:34:11PM +0000, Peter Maydell wrote: > The architecture requires that for an exception return to AArch32 the > low bits of ELR_ELx are ignored when the PC is set from them: > * if returning to Thumb mode, ignore ELR_ELx[0] > * if returning to ARM mode, ignore ELR_ELx[1:0] > > We were only squashing bit 0; also squash bit 1 if the SPSR T bit > indicates this is a return to ARM code. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/op_helper.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 5789ccb..171d6b8 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -738,7 +738,11 @@ void HELPER(exception_return)(CPUARMState *env) > } > aarch64_sync_64_to_32(env); > > - env->regs[15] = env->elr_el[cur_el] & ~0x1; > + if (spsr & CPSR_T) { > + env->regs[15] = env->elr_el[cur_el] & ~0x1; > + } else { > + env->regs[15] = env->elr_el[cur_el] & ~0x3; > + } > } else { > env->aarch64 = 1; > pstate_write(env, spsr); > -- > 1.9.1 >