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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id wu6sm18083842obb.16.2016.01.20.04.15.28 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 20 Jan 2016 04:15:28 -0800 (PST) Date: Wed, 20 Jan 2016 13:15:25 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20160120121525.GU29396@toto> References: <1453132414-8127-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4003:c06::241 Cc: qemu-arm , QEMU Developers , Patch Tracking Subject: Re: [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: MRGq/X07ammq On Mon, Jan 18, 2016 at 04:05:36PM +0000, Peter Maydell wrote: > Oops, got the qemu-arm email address wrong... Replied to the wrong email before... Reviewed-by: Edgar E. Iglesias > > On 18 January 2016 at 15:53, Peter Maydell wrote: > > The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, > > and allows those exception levels to read and write the FPEXC > > register for a lower exception level that is using AArch32. > > > > Signed-off-by: Peter Maydell > > --- > > ARM Trusted Firmware expects this to exist (as does your average > > hypervisor, I expect). > > > > target-arm/helper.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index 196c111..e8ede3f 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -2890,6 +2890,17 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, > > tlb_flush(CPU(cpu), 1); > > } > > > > +static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri) > > +{ > > + if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { > > + return CP_ACCESS_TRAP_EL2; > > + } > > + if (env->cp15.cptr_el[3] & CPTR_TFP) { > > + return CP_ACCESS_TRAP_EL3; > > + } > > + return CP_ACCESS_OK; > > +} > > + > > static const ARMCPRegInfo v8_cp_reginfo[] = { > > /* Minimal set of EL0-visible registers. This will need to be expanded > > * significantly for system emulation of AArch64 CPUs. > > @@ -3150,6 +3161,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > > .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, > > .type = ARM_CP_NO_RAW, > > .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, > > + { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, > > + .type = ARM_CP_ALIAS, > > + .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), > > + .access = PL2_RW, .accessfn = fpexc32_access }, > > REGINFO_SENTINEL > > }; > > > > -- > > 1.9.1 > > > > thanks > -- PMM