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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id l19sm18037516oig.27.2016.01.20.04.20.01 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 20 Jan 2016 04:20:02 -0800 (PST) Date: Wed, 20 Jan 2016 13:19:58 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20160120121958.GV29396@toto> References: <1453227802-9991-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1453227802-9991-1-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4003:c01::244 Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Subject: Re: [Qemu-arm] [PATCH] target-arm: Make various system registers visible to EL3 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: MIVv+cQrWsgJ On Tue, Jan 19, 2016 at 06:23:22PM +0000, Peter Maydell wrote: > The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ, > SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from > EL3 even if the CPU has no EL2 (unlike some others which are RES0 > from EL3 in that configuration). Move them from el2_cp_reginfo[] to > v8_cp_reginfo[] so they are always present. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 58 ++++++++++++++++++++++++++--------------------------- > 1 file changed, 29 insertions(+), 29 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index e8ede3f..999c617 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3166,6 +3166,35 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > .type = ARM_CP_ALIAS, > .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), > .access = PL2_RW, .accessfn = fpexc32_access }, > + { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, > + .access = PL2_RW, .resetvalue = 0, > + .writefn = dacr_write, .raw_writefn = raw_write, > + .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, > + { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, > + .access = PL2_RW, .resetvalue = 0, > + .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, > + { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_ALIAS, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, > + { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_ALIAS, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, > + { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_ALIAS, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, > + { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_ALIAS, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, > REGINFO_SENTINEL > }; > > @@ -3293,11 +3322,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), > .writefn = hcr_write }, > - { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, > - .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, > - .access = PL2_RW, .resetvalue = 0, > - .writefn = dacr_write, .raw_writefn = raw_write, > - .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, > { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_ALIAS, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, > @@ -3307,10 +3331,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .type = ARM_CP_ALIAS, > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, > - { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, > - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, > - .access = PL2_RW, .resetvalue = 0, > - .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, > { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, > @@ -3319,26 +3339,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > .access = PL2_RW, > .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, > - { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, > - .type = ARM_CP_ALIAS, > - .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, > - .access = PL2_RW, > - .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, > - { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, > - .type = ARM_CP_ALIAS, > - .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, > - .access = PL2_RW, > - .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, > - { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, > - .type = ARM_CP_ALIAS, > - .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, > - .access = PL2_RW, > - .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, > - { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, > - .type = ARM_CP_ALIAS, > - .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, > - .access = PL2_RW, > - .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, > { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, > .access = PL2_RW, .writefn = vbar_write, > -- > 1.9.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLrk8-00064h-Pr for qemu-devel@nongnu.org; Wed, 20 Jan 2016 07:20:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLrk4-0002lV-1K for qemu-devel@nongnu.org; Wed, 20 Jan 2016 07:20:08 -0500 Date: Wed, 20 Jan 2016 13:19:58 +0100 From: "Edgar E. Iglesias" Message-ID: <20160120121958.GV29396@toto> References: <1453227802-9991-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1453227802-9991-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH] target-arm: Make various system registers visible to EL3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org On Tue, Jan 19, 2016 at 06:23:22PM +0000, Peter Maydell wrote: > The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ, > SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from > EL3 even if the CPU has no EL2 (unlike some others which are RES0 > from EL3 in that configuration). Move them from el2_cp_reginfo[] to > v8_cp_reginfo[] so they are always present. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 58 ++++++++++++++++++++++++++--------------------------- > 1 file changed, 29 insertions(+), 29 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index e8ede3f..999c617 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3166,6 +3166,35 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > .type = ARM_CP_ALIAS, > .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), > .access = PL2_RW, .accessfn = fpexc32_access }, > + { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, > + .access = PL2_RW, .resetvalue = 0, > + .writefn = dacr_write, .raw_writefn = raw_write, > + .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, > + { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, > + .access = PL2_RW, .resetvalue = 0, > + .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, > + { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_ALIAS, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, > + { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_ALIAS, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, > + { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_ALIAS, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, > + { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_ALIAS, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, > REGINFO_SENTINEL > }; > > @@ -3293,11 +3322,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), > .writefn = hcr_write }, > - { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, > - .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, > - .access = PL2_RW, .resetvalue = 0, > - .writefn = dacr_write, .raw_writefn = raw_write, > - .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, > { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_ALIAS, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, > @@ -3307,10 +3331,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .type = ARM_CP_ALIAS, > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, > - { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, > - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, > - .access = PL2_RW, .resetvalue = 0, > - .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, > { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, > @@ -3319,26 +3339,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > .access = PL2_RW, > .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, > - { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, > - .type = ARM_CP_ALIAS, > - .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, > - .access = PL2_RW, > - .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, > - { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, > - .type = ARM_CP_ALIAS, > - .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, > - .access = PL2_RW, > - .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, > - { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, > - .type = ARM_CP_ALIAS, > - .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, > - .access = PL2_RW, > - .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, > - { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, > - .type = ARM_CP_ALIAS, > - .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, > - .access = PL2_RW, > - .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, > { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, > .access = PL2_RW, .writefn = vbar_write, > -- > 1.9.1 >