MIPS: ath79: TP-LINK WR1043ND: uart clk issue

[Antony Pavlov <antonynpavlov@gmail.com>]

Hi!

I have tried to run linux on TP-LINK WR1043ND v1.8.

I use branch master from git://git.linux-mips.org/pub/scm/ralf/linux

I see a problem with UART speed setup. There is no UART output after
serial port initialization. Here is the last correct linux output:

  Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
  console [ttyS0] disabled
  18020000.uart: ttyS0 at MMIO 0x18020000 (irq = 11, base_baud = 12500000) is a 8250


I can disable UART speed setup in 8250 driver:

--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -2208,6 +2208,8 @@ static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
 {
        struct uart_8250_port *up = up_to_u8250p(port);
 
+       return;
+
        /* Workaround to enable 115200 baud on OMAP1510 internal ports */
        if (is_omap1510_8250(up)) {
                if (baud == 115200) {

With this very very dirty hack linux works fine.

I suppose there is a problem in arch/mips/ath79/clock.c

I have tryed to cherry-pick your 'MIPS: ath79: Fix the ar913x reference clock rate'
and 'MIPS: ath79: Fix the ar724x clock calculation' commits from
your github ath79 branch at https://github.com/AlbanBedel/linux/tree/ath79
but these patches don't help me.

Could you please try to reproduce the problem?

-- 
Best regards,
  Antony Pavlov