From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Wed, 27 Jan 2016 22:50:51 +0100 Subject: [PATCH RFC 1/2] clk: sunxi: Add sun8i display support In-Reply-To: <20160119090901.17c64bc4afb7095bb8bd291c@free.fr> References: <9cc33c3701844a07c43ee6c0c1072be4e2073cc1.1452021349.git.moinejf@free.fr> <20160118190904.GP4581@lukather> <20160119090901.17c64bc4afb7095bb8bd291c@free.fr> Message-ID: <20160127215051.GW4317@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On Tue, Jan 19, 2016 at 09:09:01AM +0100, Jean-Francois Moine wrote: > On Mon, 18 Jan 2016 20:09:04 +0100 > Maxime Ripard wrote: > > > > +static const struct clk_ops clk_sun8i_pll3_fact_ops = { > > > + .recalc_rate = sun8i_pll3_recalc_rate, > > > + .round_rate = sun8i_pll3_round_rate, > > > + .set_rate = sun8i_pll3_set_rate, > > > +}; > > > > We have the clk-factors stuff to handle this easily, could you use > > that instead ? > > No, the sun6i/8i pll3 offers direct 297MHz and 270MHz. That's true, but so far it's something that never has been really needed. This PLL is not the same one using the fractional mode, so I guess we could extend the clk-factors to be able to deal with that. The video pll in the A10 (pll3) is also in this case, so does the A31 PLL3 and PLL4. Also note that all these clocks can reach those frequencies through what allwinner calls the integer mode, so apart from the hardware readout, we don't really need it anyway. > > As part of my DRM patches, I've added a clk-display clock that can > > handle that easily. > > > > And actually, as part of bringing up the display engine on the A33, I > > already did it: > > https://github.com/mripard/linux/commit/92b6843b5ee5b70cb2be3638df31d3eca28a4dba > > https://github.com/mripard/linux/commit/81e8ea74be5e72124eb584432bb79ff75f90d9ed > > I don't remember any patch request from yours in the Linux > mailing-lists about these developments. Indeed, I was waiting for the first DRM developments to get in before sending those for review. > > Otherwise, about this old RFC, Chen-Yu Tsai replied: > > > > Add the clock types which are used by the sun8i family for video. > > > > These clocks first appeared in the A31. The video PLL is, the display engine and tcon clocks are a bit different (mostly because of their weird parent configuration that need a muxing table). Note that I'm talking about the A23 / A33. I haven't checked for the H3. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH RFC 1/2] clk: sunxi: Add sun8i display support Date: Wed, 27 Jan 2016 22:50:51 +0100 Message-ID: <20160127215051.GW4317@lukather> References: <9cc33c3701844a07c43ee6c0c1072be4e2073cc1.1452021349.git.moinejf@free.fr> <20160118190904.GP4581@lukather> <20160119090901.17c64bc4afb7095bb8bd291c@free.fr> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0774308614==" Return-path: Received: from mail.free-electrons.com (down.free-electrons.com [37.187.137.238]) by gabe.freedesktop.org (Postfix) with ESMTP id C8DAB6E37D for ; Wed, 27 Jan 2016 13:51:03 -0800 (PST) In-Reply-To: <20160119090901.17c64bc4afb7095bb8bd291c@free.fr> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Jean-Francois Moine Cc: Emilio =?iso-8859-1?Q?L=F3pez?= , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0774308614== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="JNs4m2JFMNhdiK2v" Content-Disposition: inline --JNs4m2JFMNhdiK2v Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Tue, Jan 19, 2016 at 09:09:01AM +0100, Jean-Francois Moine wrote: > On Mon, 18 Jan 2016 20:09:04 +0100 > Maxime Ripard wrote: >=20 > > > +static const struct clk_ops clk_sun8i_pll3_fact_ops =3D { > > > + .recalc_rate =3D sun8i_pll3_recalc_rate, > > > + .round_rate =3D sun8i_pll3_round_rate, > > > + .set_rate =3D sun8i_pll3_set_rate, > > > +}; > >=20 > > We have the clk-factors stuff to handle this easily, could you use > > that instead ? >=20 > No, the sun6i/8i pll3 offers direct 297MHz and 270MHz. That's true, but so far it's something that never has been really needed. This PLL is not the same one using the fractional mode, so I guess we could extend the clk-factors to be able to deal with that. The video pll in the A10 (pll3) is also in this case, so does the A31 PLL3 and PLL4. Also note that all these clocks can reach those frequencies through what allwinner calls the integer mode, so apart from the hardware readout, we don't really need it anyway. > > As part of my DRM patches, I've added a clk-display clock that can > > handle that easily. > >=20 > > And actually, as part of bringing up the display engine on the A33, I > > already did it: > > https://github.com/mripard/linux/commit/92b6843b5ee5b70cb2be3638df31d3e= ca28a4dba > > https://github.com/mripard/linux/commit/81e8ea74be5e72124eb584432bb79ff= 75f90d9ed >=20 > I don't remember any patch request from yours in the Linux > mailing-lists about these developments. Indeed, I was waiting for the first DRM developments to get in before sending those for review. >=20 > Otherwise, about this old RFC, Chen-Yu Tsai replied: >=20 > > > Add the clock types which are used by the sun8i family for video. > >=20 > > These clocks first appeared in the A31. The video PLL is, the display engine and tcon clocks are a bit different (mostly because of their weird parent configuration that need a muxing table). Note that I'm talking about the A23 / A33. I haven't checked for the H3. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --JNs4m2JFMNhdiK2v Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWqTu7AAoJEBx+YmzsjxAgN58P/3Rd8vPQUuYptxIYMPvl6o0u G7PB12GfuJ3SnMnTc/9tlHrxkqtP8dt5EDdAqOtoigIcougjZLw3CnVtl/I7J7Lv YPZVyHg3I05xHUG1c5tFqUVgrpcYBdowVstWhgNuC/p+mDsz4vpGaXe2+6ieZwlM Z535w5+2dJEMyYEU5DX0XcYYdV1xg5f4vHJ8K3tPVjFWhy66IJNZ1Tdvvm2kkrh3 ktatEmNs4VgShC5jOOtFUcpdIbkntekQcDjqHsQohmE5z54j7ERjIxm35LzAeaqu A0FKKlSQyCFf9m4Vefd0HOvC5AOtoSrLDH211sWVhbqdWd95+lYnrdZ6h3WoFTlr 8xRwCYaqW5tCEVvivs9JGw3+qwKDFwAZ5dr4BPc6vVstJmFVcOwmt7485pQZG9Fq EOfs6IOQV6Y0+e2Ce46RFw9SYUlSKSGngepZ9OyHtTwFMDThu47XK7ktpn2ueSRZ C84/4/R5wsmGaQv+xsum3k1rRkxHw3FLtVIigUsG3VmU09XKgGbJeFhmVTOjdyXh HZ4RQNfoeFmlhEoV+XKC9bbWKeSONuc+KcOw/zw248TEZCIZ8bRisd5iSWBE/HHQ 0qomb2LSlpKKOvfRyqJzGdVGcP9VXn+fT7h2xyJCXU5XyT0bzdEsjVkaScQ7dO4J nEHkkDRdccDnv7PCkwyk =ICls -----END PGP SIGNATURE----- --JNs4m2JFMNhdiK2v-- --===============0774308614== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK --===============0774308614==--