From: Albert ARIBAUD <albert.u.boot@aribaud.net>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2] armv7: add cacheline sizes where missing
Date: Thu, 28 Jan 2016 10:03:04 +0100 [thread overview]
Message-ID: <20160128100304.3ad0d196@lilith> (raw)
In-Reply-To: <1453880771-22742-1-git-send-email-albert.u.boot@aribaud.net>
On Wed, 27 Jan 2016 08:46:11 +0100, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Some armv7 targets are missing a cache line size declaration.
> In preparation for "arm: cache: Implement cache range check for v7"
> patch, add these declarations with the appropriate value for
> the target's SoC or CPU.
>
> Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>
> Changes in v2:
> - fix include/configs/at91-sama5_common.h (Cortex-A5: 32 bytes)
Absent any complaint today, I will apply this as a prerequisite for
Marek's "arm: cache: Implement cache range check for v7".
Amicalement,
--
Albert.
next prev parent reply other threads:[~2016-01-28 9:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-27 7:46 [U-Boot] [PATCH v2] armv7: add cacheline sizes where missing Albert ARIBAUD
2016-01-28 9:03 ` Albert ARIBAUD [this message]
2016-01-29 6:39 ` Albert ARIBAUD
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