diff for duplicates of <20160205085026.GA1139@lukather> diff --git a/a/1.txt b/N1/1.txt index 327f922..cc79c0e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -11,7 +11,7 @@ On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote: > reuse the DT for 32-bit kernels as well. > This .dtsi lists the hardware that we support so far. > -> Signed-off-by: Andre Przywara <andre.przywara@arm.com> +> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> > --- > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + @@ -52,7 +52,7 @@ On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote: > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: -> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> +> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual @@ -118,28 +118,28 @@ the board enables. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; @@ -196,7 +196,7 @@ I'm guessing u-boot fixes that, can we just remove it entirely? > + clock-output-names = "osc32k"; > + }; > + -> + pll1: clk at 01c20000 { +> + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -204,7 +204,7 @@ I'm guessing u-boot fixes that, can we just remove it entirely? > + clock-output-names = "pll1"; > + }; > + -> + pll6: clk at 01c20028 { +> + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -233,7 +233,7 @@ anymore. > + clock-output-names = "pll8"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -242,7 +242,7 @@ anymore. > + critical-clocks = <0>; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -250,7 +250,7 @@ anymore. > + clock-output-names = "axi"; > + }; > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -258,7 +258,7 @@ anymore. > + clock-output-names = "ahb1"; > + }; > + -> + ahb2: ahb2_clk at 01c2005c { +> + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; @@ -266,7 +266,7 @@ anymore. > + clock-output-names = "ahb2"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -274,7 +274,7 @@ anymore. > + clock-output-names = "apb1"; > + }; > + -> + apb2: apb2_clk at 01c20058 { +> + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -282,7 +282,7 @@ anymore. > + clock-output-names = "apb2"; > + }; > + -> + bus_gates: clk at 01c20060 { +> + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,a64-bus-gates-clk", > + "allwinner,sunxi-multi-bus-gates-clk"; @@ -373,7 +373,7 @@ ended up merging it. So please use it. -> + mmc0_clk: clk at 01c20088 { +> + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; @@ -383,7 +383,7 @@ So please use it. > + "mmc0_sample"; > + }; > + -> + mmc1_clk: clk at 01c2008c { +> + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; @@ -393,7 +393,7 @@ So please use it. > + "mmc1_sample"; > + }; > + -> + mmc2_clk: clk at 01c20090 { +> + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; @@ -419,7 +419,7 @@ So please use it. > + #size-cells = <1>; > + ranges; > + -> + mmc0: mmc at 01c0f000 { +> + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&bus_gates 8>, @@ -438,7 +438,7 @@ So please use it. > + #size-cells = <0>; > + }; > + -> + mmc1: mmc at 01c10000 { +> + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&bus_gates 9>, @@ -457,7 +457,7 @@ So please use it. > + #size-cells = <0>; > + }; > + -> + mmc2: mmc at 01c11000 { +> + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&bus_gates 10>, @@ -476,7 +476,7 @@ So please use it. > + #size-cells = <0>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + compatible = "allwinner,a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -488,42 +488,42 @@ So please use it. > + interrupt-controller; > + #interrupt-cells = <2>; > + -> + uart0_pins_a: uart0 at 0 { +> + uart0_pins_a: uart0@0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart0_pins_b: uart0 at 1 { +> + uart0_pins_b: uart0@1 { > + allwinner,pins = "PF2", "PF3"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart1_pins: uart1 at 0 { +> + uart1_pins: uart1@0 { > + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart2_pins: uart2 at 0 { +> + uart2_pins: uart2@0 { > + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; > + allwinner,function = "uart2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_a: uart3 at 0 { +> + uart3_pins_a: uart3@0 { > + allwinner,pins = "PD0", "PD1"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_b: uart3 at 1 { +> + uart3_pins_b: uart3@1 { > + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -544,10 +544,3 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: Digital signature -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160205/46492fa2/attachment.sig> diff --git a/a/content_digest b/N1/content_digest index 3abcba1..3b794f7 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,24 @@ "ref\01454348370-3816-1-git-send-email-andre.przywara@arm.com\0" "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" - "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" - "Subject\0[PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "ref\01454348370-3816-11-git-send-email-andre.przywara-5wv7dgnIgG8@public.gmane.org\0" + "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Subject\0Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Fri, 5 Feb 2016 09:50:26 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>\0" + "Cc\0Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>" + linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org + Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "\01:1\0" "b\0" "Hi Andre,\n" "\n" @@ -19,7 +33,7 @@ "> reuse the DT for 32-bit kernels as well.\n" "> This .dtsi lists the hardware that we support so far.\n" "> \n" - "> Signed-off-by: Andre Przywara <andre.przywara@arm.com>\n" + "> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>\n" "> ---\n" "> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +\n" "> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +\n" @@ -60,7 +74,7 @@ "> +/*\n" "> + * Copyright (C) 2016 ARM Ltd.\n" "> + * based on the Allwinner H3 dtsi:\n" - "> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>\n" + "> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -126,28 +140,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -204,7 +218,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: clk at 01c20000 {\n" + "> +\t\tpll1: clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -212,7 +226,7 @@ "> +\t\t\tclock-output-names = \"pll1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: clk at 01c20028 {\n" + "> +\t\tpll6: clk@01c20028 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -241,7 +255,7 @@ "> +\t\t\tclock-output-names = \"pll8\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -250,7 +264,7 @@ "> +\t\t\tcritical-clocks = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -258,7 +272,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -266,7 +280,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> +\t\tahb2: ahb2_clk@01c2005c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -274,7 +288,7 @@ "> +\t\t\tclock-output-names = \"ahb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -282,7 +296,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> +\t\tapb2: apb2_clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -290,7 +304,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus_gates: clk at 01c20060 {\n" + "> +\t\tbus_gates: clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" "> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -381,7 +395,7 @@ "\n" "So please use it.\n" "\n" - "> +\t\tmmc0_clk: clk at 01c20088 {\n" + "> +\t\tmmc0_clk: clk@01c20088 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -391,7 +405,7 @@ "> +\t\t\t\t\t \"mmc0_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1_clk: clk at 01c2008c {\n" + "> +\t\tmmc1_clk: clk@01c2008c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -401,7 +415,7 @@ "> +\t\t\t\t\t \"mmc1_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: clk at 01c20090 {\n" + "> +\t\tmmc2_clk: clk@01c20090 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -427,7 +441,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tmmc0: mmc at 01c0f000 {\n" + "> +\t\tmmc0: mmc@01c0f000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c0f000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 8>,\n" @@ -446,7 +460,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1: mmc at 01c10000 {\n" + "> +\t\tmmc1: mmc@01c10000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c10000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 9>,\n" @@ -465,7 +479,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2: mmc at 01c11000 {\n" + "> +\t\tmmc2: mmc@01c11000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c11000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 10>,\n" @@ -484,7 +498,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,a64-pinctrl\";\n" "> +\t\t\treg = <0x01c20800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -496,42 +510,42 @@ "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <2>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> +\t\t\tuart0_pins_a: uart0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + "> +\t\t\tuart0_pins_b: uart0@1 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1_pins: uart1 at 0 {\n" + "> +\t\t\tuart1_pins: uart1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" "> +\t\t\t\tallwinner,function = \"uart1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2_pins: uart2 at 0 {\n" + "> +\t\t\tuart2_pins: uart2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" "> +\t\t\t\tallwinner,function = \"uart2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + "> +\t\t\tuart3_pins_a: uart3@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_b: uart3 at 1 {\n" + "> +\t\t\tuart3_pins_b: uart3@1 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -551,13 +565,6 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: Digital signature\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160205/46492fa2/attachment.sig> + http://free-electrons.com -21339f49a9b2821b93bef53a6e3708980565a2224965da4077af6635a90e4129 +a262e0092ff3170fda96d0e2c5f00f11f98cd6e69b61122ef7f3e2d2a1efd266
diff --git a/a/1.txt b/N2/1.txt index 327f922..e198387 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -118,28 +118,28 @@ the board enables. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; @@ -196,7 +196,7 @@ I'm guessing u-boot fixes that, can we just remove it entirely? > + clock-output-names = "osc32k"; > + }; > + -> + pll1: clk at 01c20000 { +> + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -204,7 +204,7 @@ I'm guessing u-boot fixes that, can we just remove it entirely? > + clock-output-names = "pll1"; > + }; > + -> + pll6: clk at 01c20028 { +> + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -233,7 +233,7 @@ anymore. > + clock-output-names = "pll8"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -242,7 +242,7 @@ anymore. > + critical-clocks = <0>; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -250,7 +250,7 @@ anymore. > + clock-output-names = "axi"; > + }; > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -258,7 +258,7 @@ anymore. > + clock-output-names = "ahb1"; > + }; > + -> + ahb2: ahb2_clk at 01c2005c { +> + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; @@ -266,7 +266,7 @@ anymore. > + clock-output-names = "ahb2"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -274,7 +274,7 @@ anymore. > + clock-output-names = "apb1"; > + }; > + -> + apb2: apb2_clk at 01c20058 { +> + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -282,7 +282,7 @@ anymore. > + clock-output-names = "apb2"; > + }; > + -> + bus_gates: clk at 01c20060 { +> + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,a64-bus-gates-clk", > + "allwinner,sunxi-multi-bus-gates-clk"; @@ -373,7 +373,7 @@ ended up merging it. So please use it. -> + mmc0_clk: clk at 01c20088 { +> + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; @@ -383,7 +383,7 @@ So please use it. > + "mmc0_sample"; > + }; > + -> + mmc1_clk: clk at 01c2008c { +> + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; @@ -393,7 +393,7 @@ So please use it. > + "mmc1_sample"; > + }; > + -> + mmc2_clk: clk at 01c20090 { +> + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; @@ -419,7 +419,7 @@ So please use it. > + #size-cells = <1>; > + ranges; > + -> + mmc0: mmc at 01c0f000 { +> + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&bus_gates 8>, @@ -438,7 +438,7 @@ So please use it. > + #size-cells = <0>; > + }; > + -> + mmc1: mmc at 01c10000 { +> + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&bus_gates 9>, @@ -457,7 +457,7 @@ So please use it. > + #size-cells = <0>; > + }; > + -> + mmc2: mmc at 01c11000 { +> + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&bus_gates 10>, @@ -476,7 +476,7 @@ So please use it. > + #size-cells = <0>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + compatible = "allwinner,a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -488,42 +488,42 @@ So please use it. > + interrupt-controller; > + #interrupt-cells = <2>; > + -> + uart0_pins_a: uart0 at 0 { +> + uart0_pins_a: uart0@0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart0_pins_b: uart0 at 1 { +> + uart0_pins_b: uart0@1 { > + allwinner,pins = "PF2", "PF3"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart1_pins: uart1 at 0 { +> + uart1_pins: uart1@0 { > + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart2_pins: uart2 at 0 { +> + uart2_pins: uart2@0 { > + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; > + allwinner,function = "uart2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_a: uart3 at 0 { +> + uart3_pins_a: uart3@0 { > + allwinner,pins = "PD0", "PD1"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_b: uart3 at 1 { +> + uart3_pins_b: uart3@1 { > + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -544,10 +544,3 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: Digital signature -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160205/46492fa2/attachment.sig> diff --git a/N2/2.bin b/N2/2.bin new file mode 100644 index 0000000..6347e00 --- /dev/null +++ b/N2/2.bin @@ -0,0 +1,17 @@ +-----BEGIN PGP SIGNATURE----- +Version: GnuPG v1 + +iQIcBAEBAgAGBQJWtGJSAAoJEBx+YmzsjxAgs+MQAJbo9wI16m3P9NocG/7F5GzS +36e95acBEKRZpWTZCdl22m7QWBPPx+0ecduxeaS6vFkEP2bRbM0zDaYFw3WC6sc7 +49U72evhEZGkJSyGE5v9M0/0K7iVen4WbKM1wqRiBke9bp23LTaTKFXG43RJc8E0 +cF6pnSJUkTvJpkQSDkS3Sryb+XkEP1ytwvUcmld7/bw6xG/D66lh1+oAKukqXStt +czJN+7/7B626mPq+Bxgm2YnKXMWi0X1OlRyZiQQtESyQf9llyuVYKPgo49Jb+//X +pkVEQy0ueZaYXRpgtJQpMibmiclaKHHYZ9ZDwd2x7/CJoQLlX5L1zSssw3SPF5Yf +eGnsgg1VIeU8diJI6PwCHfaQI38GGltyzU6zfhkqZVwHJzcUtiKEBHj7IiW9vrQI +v2d/YhMBCA4Zj8NUr9Mtk5JU1Rpu6dpjirDBXv1XmDBYfeVkqX/j9/jF/SCH2q3g +VrfCB2ZmcZvd0Fwa7ZaLUEtrXZ1BnARxyOfE/WXzu0Zd79ibAF13a7JNl1YoCU51 +LuAm8FG2kOfhPBfVoYvjiol0hoR4xsXubldm+Iye25anuJZ5nAcnBQuyCozHsG6l +ZhQRAXuyMb4iZ7vsDLAa6fHGzbkBwR3h9Fh0HAKoE5BKpOcBOmD+19OEnJABzDrB +2sUBnIBir4Cm1UcrUdjW +=eVVd +-----END PGP SIGNATURE----- diff --git a/N2/2.hdr b/N2/2.hdr new file mode 100644 index 0000000..3237378 --- /dev/null +++ b/N2/2.hdr @@ -0,0 +1,2 @@ +Content-Type: application/pgp-signature; name="signature.asc" +Content-Description: Digital signature diff --git a/a/content_digest b/N2/content_digest index 3abcba1..a28e654 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,23 @@ "ref\01454348370-3816-1-git-send-email-andre.przywara@arm.com\0" "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" - "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" - "Subject\0[PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "From\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" + "Subject\0Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Fri, 5 Feb 2016 09:50:26 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Andre Przywara <andre.przywara@arm.com>\0" + "Cc\0Chen-Yu Tsai <wens@csie.org>" + linux-sunxi@googlegroups.com + Arnd Bergmann <arnd@arndb.de> + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + Rob Herring <robh+dt@kernel.org> + Pawel Moll <pawel.moll@arm.com> + Mark Rutland <mark.rutland@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Kumar Gala <galak@codeaurora.org> + " devicetree@vger.kernel.org\0" + "\01:1\0" "b\0" "Hi Andre,\n" "\n" @@ -126,28 +139,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -204,7 +217,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: clk at 01c20000 {\n" + "> +\t\tpll1: clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -212,7 +225,7 @@ "> +\t\t\tclock-output-names = \"pll1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: clk at 01c20028 {\n" + "> +\t\tpll6: clk@01c20028 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -241,7 +254,7 @@ "> +\t\t\tclock-output-names = \"pll8\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -250,7 +263,7 @@ "> +\t\t\tcritical-clocks = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -258,7 +271,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -266,7 +279,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> +\t\tahb2: ahb2_clk@01c2005c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -274,7 +287,7 @@ "> +\t\t\tclock-output-names = \"ahb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -282,7 +295,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> +\t\tapb2: apb2_clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -290,7 +303,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus_gates: clk at 01c20060 {\n" + "> +\t\tbus_gates: clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" "> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -381,7 +394,7 @@ "\n" "So please use it.\n" "\n" - "> +\t\tmmc0_clk: clk at 01c20088 {\n" + "> +\t\tmmc0_clk: clk@01c20088 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -391,7 +404,7 @@ "> +\t\t\t\t\t \"mmc0_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1_clk: clk at 01c2008c {\n" + "> +\t\tmmc1_clk: clk@01c2008c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -401,7 +414,7 @@ "> +\t\t\t\t\t \"mmc1_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: clk at 01c20090 {\n" + "> +\t\tmmc2_clk: clk@01c20090 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -427,7 +440,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tmmc0: mmc at 01c0f000 {\n" + "> +\t\tmmc0: mmc@01c0f000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c0f000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 8>,\n" @@ -446,7 +459,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1: mmc at 01c10000 {\n" + "> +\t\tmmc1: mmc@01c10000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c10000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 9>,\n" @@ -465,7 +478,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2: mmc at 01c11000 {\n" + "> +\t\tmmc2: mmc@01c11000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c11000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 10>,\n" @@ -484,7 +497,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,a64-pinctrl\";\n" "> +\t\t\treg = <0x01c20800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -496,42 +509,42 @@ "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <2>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> +\t\t\tuart0_pins_a: uart0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + "> +\t\t\tuart0_pins_b: uart0@1 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1_pins: uart1 at 0 {\n" + "> +\t\t\tuart1_pins: uart1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" "> +\t\t\t\tallwinner,function = \"uart1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2_pins: uart2 at 0 {\n" + "> +\t\t\tuart2_pins: uart2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" "> +\t\t\t\tallwinner,function = \"uart2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + "> +\t\t\tuart3_pins_a: uart3@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_b: uart3 at 1 {\n" + "> +\t\t\tuart3_pins_b: uart3@1 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -551,13 +564,27 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: Digital signature\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160205/46492fa2/attachment.sig> + http://free-electrons.com + "\01:2\0" + "fn\0signature.asc\0" + "d\0Digital signature\0" + "b\0" + "-----BEGIN PGP SIGNATURE-----\n" + "Version: GnuPG v1\n" + "\n" + "iQIcBAEBAgAGBQJWtGJSAAoJEBx+YmzsjxAgs+MQAJbo9wI16m3P9NocG/7F5GzS\n" + "36e95acBEKRZpWTZCdl22m7QWBPPx+0ecduxeaS6vFkEP2bRbM0zDaYFw3WC6sc7\n" + "49U72evhEZGkJSyGE5v9M0/0K7iVen4WbKM1wqRiBke9bp23LTaTKFXG43RJc8E0\n" + "cF6pnSJUkTvJpkQSDkS3Sryb+XkEP1ytwvUcmld7/bw6xG/D66lh1+oAKukqXStt\n" + "czJN+7/7B626mPq+Bxgm2YnKXMWi0X1OlRyZiQQtESyQf9llyuVYKPgo49Jb+//X\n" + "pkVEQy0ueZaYXRpgtJQpMibmiclaKHHYZ9ZDwd2x7/CJoQLlX5L1zSssw3SPF5Yf\n" + "eGnsgg1VIeU8diJI6PwCHfaQI38GGltyzU6zfhkqZVwHJzcUtiKEBHj7IiW9vrQI\n" + "v2d/YhMBCA4Zj8NUr9Mtk5JU1Rpu6dpjirDBXv1XmDBYfeVkqX/j9/jF/SCH2q3g\n" + "VrfCB2ZmcZvd0Fwa7ZaLUEtrXZ1BnARxyOfE/WXzu0Zd79ibAF13a7JNl1YoCU51\n" + "LuAm8FG2kOfhPBfVoYvjiol0hoR4xsXubldm+Iye25anuJZ5nAcnBQuyCozHsG6l\n" + "ZhQRAXuyMb4iZ7vsDLAa6fHGzbkBwR3h9Fh0HAKoE5BKpOcBOmD+19OEnJABzDrB\n" + "2sUBnIBir4Cm1UcrUdjW\n" + "=eVVd\n" + "-----END PGP SIGNATURE-----\n" -21339f49a9b2821b93bef53a6e3708980565a2224965da4077af6635a90e4129 +4990af14339a83cffac925a55699560dd2a0e2f20befec7143f92036861bcae7
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