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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id x13sm4673518pfa.72.2016.02.06.08.10.00 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Sat, 06 Feb 2016 08:10:01 -0800 (PST) Date: Sat, 6 Feb 2016 17:03:22 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20160206160322.GD3913@toto> References: <1454506721-11843-1-git-send-email-peter.maydell@linaro.org> <1454506721-11843-4-git-send-email-peter.maydell@linaro.org> <20160206121756.GC3913@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::243 Cc: qemu-arm , QEMU Developers , Patch Tracking Subject: Re: [Qemu-arm] [PATCH 3/7] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: FHO6bl4p2Ylj On Sat, Feb 06, 2016 at 01:48:19PM +0000, Peter Maydell wrote: > On 6 February 2016 at 12:17, Edgar E. Iglesias wrote: > > It seems to me like if EL3 is running in AArch32, then we shouldn't > > trap accesses from Secure EL1 but I can't find that logic. Am I missing > > something? > > If EL3 is running in AArch32 then there is no Secure EL1 -- all > of SVC, IRQ, and the other PL1 modes run at EL3 privilege, > and arm_current_el() will return 3 in this situation. Yep, I keep forgetting that for AArch32... Cheers, Edgar From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aS5R2-00018D-B6 for qemu-devel@nongnu.org; Sat, 06 Feb 2016 11:10:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aS5Qx-0006P6-8H for qemu-devel@nongnu.org; Sat, 06 Feb 2016 11:10:08 -0500 Date: Sat, 6 Feb 2016 17:03:22 +0100 From: "Edgar E. Iglesias" Message-ID: <20160206160322.GD3913@toto> References: <1454506721-11843-1-git-send-email-peter.maydell@linaro.org> <1454506721-11843-4-git-send-email-peter.maydell@linaro.org> <20160206121756.GC3913@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH 3/7] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm , QEMU Developers , Patch Tracking On Sat, Feb 06, 2016 at 01:48:19PM +0000, Peter Maydell wrote: > On 6 February 2016 at 12:17, Edgar E. Iglesias wrote: > > It seems to me like if EL3 is running in AArch32, then we shouldn't > > trap accesses from Secure EL1 but I can't find that logic. Am I missing > > something? > > If EL3 is running in AArch32 then there is no Secure EL1 -- all > of SVC, IRQ, and the other PL1 modes run at EL3 privilege, > and arm_current_el() will return 3 in this situation. Yep, I keep forgetting that for AArch32... Cheers, Edgar