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From: Edward Cragg <edward.cragg@codethink.co.uk>
To: Eric Auger <eric.auger@linaro.org>
Cc: kvmarm@lists.cs.columbia.edu
Subject: Re: PCIe passthrough support on ARM
Date: Mon, 8 Feb 2016 17:01:58 +0000	[thread overview]
Message-ID: <20160208170158.GD31029@codethink.co.uk> (raw)
In-Reply-To: <56B89082.5010804@linaro.org>

On Mon, Feb 08, 2016 at 01:56:34PM +0100, Eric Auger wrote:
> > Do you mean the GIC itself? From registers, it appears to be a standard ARM
> > GIC, though i'm not sure exactly which one yet. However, it's stated in the
> > processor's datasheet that legacy interrupts aren't supported. It's one of the
> > newer Samsung Exynos processors.
> I meant GICv2m (featuring single or multiple MSI frames) or GICv3 ITS or
> any other proprietary interrupt controller IP supporting MSIs.

>From the manual, it seems from the reset values for the identification
registers that it is most likely a GICv2.

If we continue with this project, and once we get access to hardware, we'd be
very interested in helping you with testing this.

Thanks,

Ed

      reply	other threads:[~2016-02-08 16:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-04 16:53 PCIe passthrough support on ARM Edward Cragg
2016-02-04 17:30 ` Eric Auger
2016-02-08 11:13   ` Edward Cragg
2016-02-08 12:56     ` Eric Auger
2016-02-08 17:01       ` Edward Cragg [this message]

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