From: Brian Norris <computersforpeace@gmail.com>
To: Kamal Dasu <kdasu.kdev@gmail.com>
Cc: "Rafał Miłecki" <zajec5@gmail.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"Hauke Mehrtens" <hauke@hauke-m.de>,
bcm-kernel-feedback-list <bcm-kernel-feedback-list@broadcom.com>
Subject: Re: brcmnand (iproc): bitflips and ECC errors due to ignored ECC config
Date: Mon, 8 Feb 2016 11:21:11 -0800 [thread overview]
Message-ID: <20160208192111.GA62607@google.com> (raw)
In-Reply-To: <CAC=U0a1vj1020X8BjvYGSOi7GrJCAad3A8wCeosuEo+7i4Rk3A@mail.gmail.com>
On Mon, Feb 08, 2016 at 02:15:16PM -0500, Kamal Dasu wrote:
> When SECTOR_SIZE = 512B, SPARE_AREA_SIZE = 16, ECC_LEVEL = 15 enables
> 1-bit Hamming ECC protection. So the ecc_level field is the SoC
> internal representation for 1-bit hamming. If you mean by "removing
> handling" you made strength=ecc_level=1, then you are now using 1-bit
> BCH.
It kinda sounds like Rafal is suggesting this product uses 1-bit BCH.
I didn't even remember such a thing existed on this controller.
Unfortunately, we don't really have a way to clearly differentiate 1-bit
Hamming and 1-bit BCH in DT, do we? Both could equally well be described
by:
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
Maybe we need a custom BRCM property?
Brian
next prev parent reply other threads:[~2016-02-08 19:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-25 12:59 brcmnand (iproc): bitflips and ECC errors due to ignored ECC config Rafał Miłecki
2016-02-08 9:54 ` Rafał Miłecki
2016-02-08 19:15 ` Kamal Dasu
2016-02-08 19:21 ` Brian Norris [this message]
2016-02-08 20:05 ` Kamal Dasu
2016-02-12 12:06 ` Rafał Miłecki
2016-02-12 16:16 ` Kamal Dasu
2016-02-12 18:10 ` Rafał Miłecki
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