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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id o17sm20202247pfj.50.2016.02.12.07.19.28 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 12 Feb 2016 07:19:30 -0800 (PST) Date: Fri, 12 Feb 2016 16:17:02 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20160212151702.GJ31433@toto> References: <1455217909-28317-1-git-send-email-peter.maydell@linaro.org> <1455217909-28317-5-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1455217909-28317-5-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::244 Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Subject: Re: [Qemu-arm] [PATCH 4/4] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 3FzZQ7nb24hF On Thu, Feb 11, 2016 at 07:11:49PM +0000, Peter Maydell wrote: > Make get_r13_banked() raise an exception at runtime for the > corner case of SRS from System mode, so that we can UNDEF it; > this brings us in to line with the ARM ARM's set of permitted > CONSTRAINED UNPREDICTABLE choices. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Peter Maydell > --- > target-arm/op_helper.c | 8 ++++++++ > target-arm/translate.c | 9 +++++---- > 2 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 05f97a7..8183108 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -474,6 +474,14 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) > #if defined(CONFIG_USER_ONLY) > g_assert_not_reached(); > #endif > + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { > + /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF. > + * Other UNPREDICTABLE and UNDEF cases were caught at translate time. > + */ > + raise_exception(env, EXCP_UDEF, syn_uncategorized(), > + exception_target_el(env)); > + } > + > if ((env->uncached_cpsr & CPSR_M) == mode) { > return env->regs[13]; > } else { > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 7bceb05..e69145d 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7590,10 +7590,7 @@ static void gen_srs(DisasContext *s, > * -- not a valid mode number > * -- a mode that's at a higher exception level > * -- Monitor, if we are Non-secure > - * For the UNPREDICTABLE cases we choose to UNDEF, except that for > - * "current mode is System" we will write a garbage SPSR. > - * (This is because we don't have access to our current mode here > - * and would have to do a runtime check to UNDEF for System.) > + * For the UNPREDICTABLE cases we choose to UNDEF. > */ > if (s->current_el == 1 && !s->ns) { > gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3); > @@ -7639,6 +7636,9 @@ static void gen_srs(DisasContext *s, > > addr = tcg_temp_new_i32(); > tmp = tcg_const_i32(mode); > + /* get_r13_banked() will raise an exception if called from System mode */ > + gen_set_condexec(s); > + gen_set_pc_im(s, s->pc - 4); > gen_helper_get_r13_banked(addr, cpu_env, tmp); > tcg_temp_free_i32(tmp); > switch (amode) { > @@ -7688,6 +7688,7 @@ static void gen_srs(DisasContext *s, > tcg_temp_free_i32(tmp); > } > tcg_temp_free_i32(addr); > + s->is_jmp = DISAS_UPDATE; > } > > static void disas_arm_insn(DisasContext *s, unsigned int insn) > -- > 1.9.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48447) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aUFVQ-0003qT-Ph for qemu-devel@nongnu.org; Fri, 12 Feb 2016 10:19:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aUFVL-0004No-Ve for qemu-devel@nongnu.org; Fri, 12 Feb 2016 10:19:36 -0500 Date: Fri, 12 Feb 2016 16:17:02 +0100 From: "Edgar E. Iglesias" Message-ID: <20160212151702.GJ31433@toto> References: <1455217909-28317-1-git-send-email-peter.maydell@linaro.org> <1455217909-28317-5-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1455217909-28317-5-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 4/4] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Sergey Fedorov , qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org On Thu, Feb 11, 2016 at 07:11:49PM +0000, Peter Maydell wrote: > Make get_r13_banked() raise an exception at runtime for the > corner case of SRS from System mode, so that we can UNDEF it; > this brings us in to line with the ARM ARM's set of permitted > CONSTRAINED UNPREDICTABLE choices. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Peter Maydell > --- > target-arm/op_helper.c | 8 ++++++++ > target-arm/translate.c | 9 +++++---- > 2 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 05f97a7..8183108 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -474,6 +474,14 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) > #if defined(CONFIG_USER_ONLY) > g_assert_not_reached(); > #endif > + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { > + /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF. > + * Other UNPREDICTABLE and UNDEF cases were caught at translate time. > + */ > + raise_exception(env, EXCP_UDEF, syn_uncategorized(), > + exception_target_el(env)); > + } > + > if ((env->uncached_cpsr & CPSR_M) == mode) { > return env->regs[13]; > } else { > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 7bceb05..e69145d 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7590,10 +7590,7 @@ static void gen_srs(DisasContext *s, > * -- not a valid mode number > * -- a mode that's at a higher exception level > * -- Monitor, if we are Non-secure > - * For the UNPREDICTABLE cases we choose to UNDEF, except that for > - * "current mode is System" we will write a garbage SPSR. > - * (This is because we don't have access to our current mode here > - * and would have to do a runtime check to UNDEF for System.) > + * For the UNPREDICTABLE cases we choose to UNDEF. > */ > if (s->current_el == 1 && !s->ns) { > gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3); > @@ -7639,6 +7636,9 @@ static void gen_srs(DisasContext *s, > > addr = tcg_temp_new_i32(); > tmp = tcg_const_i32(mode); > + /* get_r13_banked() will raise an exception if called from System mode */ > + gen_set_condexec(s); > + gen_set_pc_im(s, s->pc - 4); > gen_helper_get_r13_banked(addr, cpu_env, tmp); > tcg_temp_free_i32(tmp); > switch (amode) { > @@ -7688,6 +7688,7 @@ static void gen_srs(DisasContext *s, > tcg_temp_free_i32(tmp); > } > tcg_temp_free_i32(addr); > + s->is_jmp = DISAS_UPDATE; > } > > static void disas_arm_insn(DisasContext *s, unsigned int insn) > -- > 1.9.1 >