From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Fix hpd live status bits for g4x Date: Mon, 15 Feb 2016 19:13:51 +0200 Message-ID: <20160215171351.GX23290@intel.com> References: <1455127145-20087-1-git-send-email-ville.syrjala@linux.intel.com> <20160211100358.GR11240@phenom.ffwll.local> <87vb5uqwa4.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id CC97A6E6BA for ; Mon, 15 Feb 2016 17:13:55 +0000 (UTC) Content-Disposition: inline In-Reply-To: <87vb5uqwa4.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jani Nikula Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Nick Bowler List-Id: intel-gfx@lists.freedesktop.org T24gRnJpLCBGZWIgMTIsIDIwMTYgYXQgMDg6MjY6MjdBTSArMDIwMCwgSmFuaSBOaWt1bGEgd3Jv dGU6Cj4gT24gVGh1LCAxMSBGZWIgMjAxNiwgRGFuaWVsIFZldHRlciA8ZGFuaWVsQGZmd2xsLmNo PiB3cm90ZToKPiA+IE9uIFdlZCwgRmViIDEwLCAyMDE2IGF0IDA3OjU5OjA1UE0gKzAyMDAsIHZp bGxlLnN5cmphbGFAbGludXguaW50ZWwuY29tIHdyb3RlOgo+ID4+IEZyb206IFZpbGxlIFN5cmrD pGzDpCA8dmlsbGUuc3lyamFsYUBsaW51eC5pbnRlbC5jb20+Cj4gPj4gCj4gPj4gTG9va3MgbGlr ZSBnNHggaHBkIGxpdmUgc3RhdHVzIGJpdHMgYWN0dWFsbHkgYWdyZWUgd2l0aCB0aGUgc3BlYy4g QXQKPiA+PiBsZWFzdCB0aGV5IGRvIG9uIHRoZSBtYWNoaW5lIEkgaGF2ZSwgYW5kIGFwcGFyZW50 bHkgb24gTmljayBCb3dsZXIncwo+ID4+IGc0eCBhcyB3ZWxsLgo+ID4+IAo+ID4+IFNvIGdtNDUg bWF5IGJlIHRoZSBvbmx5IHBsYXRmb3JtIHdoZXJlIHRoZXkgZG9uJ3QgYWdyZWUuIEF0IGxlYXN0 Cj4gPj4gdGhhdCBzZWVtcyB0byBiZSB0aGUgY2FzZSBiYXNlZCBvbiB0aGUgKHNvbWV3aGF0IGlu Y29tcGxldGUpCj4gPj4gbG9ncy9kdW1wcyBpbiBbMV0sIGFuZCBEYW5pZWwgaGFzIGFsc28gdGVz dGVkIHRoaXMgb24gaGlzIGdtNDUKPiA+PiBzb21ldGltZSBpbiB0aGUgcGFzdC4KPiA+PiAKPiA+ PiBTbyBsZXQncyBjaGFuZ2UgdGhlIGJpdHMgdG8gbWF0Y2ggdGhlIHNwZWMgb24gZzR4LiBUaGF0 IGFjdHVhbGx5IG1ha2VzCj4gPj4gdGhlIGc0eCBiaXRzIGlkZW50aWNhbCB0byB2bHYvY2h2IHNv IHdlIGNhbiBqdXN0IHNoYXJlIHRoZSBjb2RlCj4gPj4gYmV0d2VlbiB0aG9zZSBwbGF0Zm9ybXMs IGxlYXZpbmcgZ200NSBhcyB0aGUgc3BlY2lhbCBjYXNlLgo+ID4+IAo+ID4+IFsxXSBodHRwczov L2J1Z3ppbGxhLmtlcm5lbC5vcmcvc2hvd19idWcuY2dpP2lkPTUyMzYxCj4gPj4gCj4gPj4gQ2M6 IFNoYXNoYW5rIFNoYXJtYSA8c2hhc2hhbmsuc2hhcm1hQGludGVsLmNvbT4KPiA+PiBDYzogU29u aWthIEppbmRhbCA8c29uaWthLmppbmRhbEBpbnRlbC5jb20+Cj4gPj4gQ2M6IERhbmllbCBWZXR0 ZXIgPGRhbmllbC52ZXR0ZXJAZmZ3bGwuY2g+Cj4gPj4gQ2M6IEphbmkgTmlrdWxhIDxqYW5pLm5p a3VsYUBsaW51eC5pbnRlbC5jb20+Cj4gPj4gQ2M6IE5pY2sgQm93bGVyIDxuYm93bGVyQGRyYWNv bnguY2E+Cj4gPj4gUmVmZXJlbmNlczogaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvYXJj aGl2ZXMvZHJpLWRldmVsLzIwMTYtRmVicnVhcnkvMTAwMzgyLmh0bWwKPiA+PiBSZXBvcnRlZC1i eTogTmljayBCb3dsZXIgPG5ib3dsZXJAZHJhY29ueC5jYT4KPiA+PiBDYzogc3RhYmxlQHZnZXIu a2VybmVsLm9yZwo+ID4+IEZpeGVzOiAyMzdlZDg2YzY5M2QgKCJkcm0vaTkxNTogQ2hlY2sgbGl2 ZSBzdGF0dXMgYmVmb3JlIHJlYWRpbmcgZWRpZCIpCj4gPj4gU2lnbmVkLW9mZi1ieTogVmlsbGUg U3lyasOkbMOkIDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPiA+Cj4gPiBZZWFoIEkn bSBob3BlZnVsIHRoaXMgd2lsbCB3b3JrLiBSZXZpZXdlZC1ieTogRGFuaWVsIFZldHRlciA8ZGFu aWVsLnZldHRlckBmZndsbC5jaD4KPiA+Cj4gPiBTaW5jZSBDSSBpcyBkb3duIGFuZCB0aGlzIGlz IHN1cGVyIHJlc3RyaWN0ZWQgaW1wYWN0IGFuZCBmaXhpbmcgYQo+ID4gcmVncmVzc2lvbiBJJ20g dm90aW5nIHRoYXQgd2UnbGwgcGljayBpdCB1cCByaWdodCBhd2F5LiBKYW5pLCBhcmUgeW91IG9r Cj4gPiB3aXRoIHRoYXQ/Cj4gCj4gQWNrLgoKIlJpZ2h0IGF3YXkiIHdhcyBzbGlnaHRseSBkZWFs eWVkIGJ5IG15IGxhenluZXNzLgpBbnl3YXksIHB1c2hlZCB0aGlzIHRvIGRpbnEuIFRoYW5rcyBm b3IgdGhlIHJldmlldy4KCj4gCj4gPiAtRGFuaWVsCj4gPgo+ID4+IC0tLQo+ID4+ICBkcml2ZXJz L2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oIHwgMTUgKysrKysrKystLS0tLS0tCj4gPj4gIGRyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX2RwLmMgfCAxNCArKysrKysrLS0tLS0tLQo+ID4+ICAyIGZp bGVzIGNoYW5nZWQsIDE1IGluc2VydGlvbnMoKyksIDE0IGRlbGV0aW9ucygtKQo+ID4+IAo+ID4+ IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oIGIvZHJpdmVycy9n cHUvZHJtL2k5MTUvaTkxNV9yZWcuaAo+ID4+IGluZGV4IDE4OGFkNWRlMDIwZi4uNjc4ZmFhOTU3 ZTc1IDEwMDY0NAo+ID4+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgKPiA+ PiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oCj4gPj4gQEAgLTMyOTYsMTkg KzMyOTYsMjAgQEAgZW51bSBza2xfZGlzcF9wb3dlcl93ZWxscyB7Cj4gPj4gIAo+ID4+ICAjZGVm aW5lIFBPUlRfSE9UUExVR19TVEFUCV9NTUlPKGRldl9wcml2LT5pbmZvLmRpc3BsYXlfbW1pb19v ZmZzZXQgKyAweDYxMTE0KQo+ID4+ICAvKgo+ID4+IC0gKiBIRE1JL0RQIGJpdHMgYXJlIGdlbjQr Cj4gPj4gKyAqIEhETUkvRFAgYml0cyBhcmUgZzR4Kwo+ID4+ICAgKgo+ID4+ICAgKiBXQVJOSU5H OiBCc3BlYyBmb3IgaHBkIHN0YXR1cyBiaXRzIG9uIGdlbjQgc2VlbXMgdG8gYmUgY29tcGxldGVs eSBjb25mdXNlZC4KPiA+PiAgICogUGxlYXNlIGNoZWNrIHRoZSBkZXRhaWxlZCBsb3JlIGluIHRo ZSBjb21taXQgbWVzc2FnZSBmb3IgZm9yIGV4cGVyaW1lbnRhbAo+ID4+ICAgKiBldmlkZW5jZS4K PiA+PiAgICovCj4gPj4gLSNkZWZpbmUgICBQT1JURF9IT1RQTFVHX0xJVkVfU1RBVFVTX0c0WAkJ KDEgPDwgMjkpCj4gPj4gKy8qIEJzcGVjIHNheXMgR000NSBzaG91bGQgbWF0Y2ggRzRYL1ZMVi9D SFYsIGJ1dCByZWFsaXR5IGRpc2FncmVlcyAqLwo+ID4+ICsjZGVmaW5lICAgUE9SVERfSE9UUExV R19MSVZFX1NUQVRVU19HTTQ1CSgxIDw8IDI5KQo+ID4+ICsjZGVmaW5lICAgUE9SVENfSE9UUExV R19MSVZFX1NUQVRVU19HTTQ1CSgxIDw8IDI4KQo+ID4+ICsjZGVmaW5lICAgUE9SVEJfSE9UUExV R19MSVZFX1NUQVRVU19HTTQ1CSgxIDw8IDI3KQo+ID4+ICsvKiBHNFgvVkxWL0NIViBEUC9IRE1J IGJpdHMgYWdhaW4gbWF0Y2ggQnNwZWMgKi8KPiA+PiArI2RlZmluZSAgIFBPUlREX0hPVFBMVUdf TElWRV9TVEFUVVNfRzRYCQkoMSA8PCAyNykKPiA+PiAgI2RlZmluZSAgIFBPUlRDX0hPVFBMVUdf TElWRV9TVEFUVVNfRzRYCQkoMSA8PCAyOCkKPiA+PiAtI2RlZmluZSAgIFBPUlRCX0hPVFBMVUdf TElWRV9TVEFUVVNfRzRYCQkoMSA8PCAyNykKPiA+PiAtLyogVkxWIERQL0hETUkgYml0cyBhZ2Fp biBtYXRjaCBCc3BlYyAqLwo+ID4+IC0jZGVmaW5lICAgUE9SVERfSE9UUExVR19MSVZFX1NUQVRV U19WTFYJCSgxIDw8IDI3KQo+ID4+IC0jZGVmaW5lICAgUE9SVENfSE9UUExVR19MSVZFX1NUQVRV U19WTFYJCSgxIDw8IDI4KQo+ID4+IC0jZGVmaW5lICAgUE9SVEJfSE9UUExVR19MSVZFX1NUQVRV U19WTFYJCSgxIDw8IDI5KQo+ID4+ICsjZGVmaW5lICAgUE9SVEJfSE9UUExVR19MSVZFX1NUQVRV U19HNFgJCSgxIDw8IDI5KQo+ID4+ICAjZGVmaW5lICAgUE9SVERfSE9UUExVR19JTlRfU1RBVFVT CQkoMyA8PCAyMSkKPiA+PiAgI2RlZmluZSAgIFBPUlREX0hPVFBMVUdfSU5UX0xPTkdfUFVMU0UJ CSgyIDw8IDIxKQo+ID4+ICAjZGVmaW5lICAgUE9SVERfSE9UUExVR19JTlRfU0hPUlRfUFVMU0UJ CSgxIDw8IDIxKQo+ID4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9k cC5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHAuYwo+ID4+IGluZGV4IGEwNzNmMDRh NTMzMC4uYmJlMTg5OTZlZmU2IDEwMDY0NAo+ID4+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX2RwLmMKPiA+PiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcC5jCj4g Pj4gQEAgLTQ0OTAsMjAgKzQ0OTAsMjAgQEAgc3RhdGljIGJvb2wgZzR4X2RpZ2l0YWxfcG9ydF9j b25uZWN0ZWQoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LAo+ID4+ICAJcmV0dXJu IEk5MTVfUkVBRChQT1JUX0hPVFBMVUdfU1RBVCkgJiBiaXQ7Cj4gPj4gIH0KPiA+PiAgCj4gPj4g LXN0YXRpYyBib29sIHZsdl9kaWdpdGFsX3BvcnRfY29ubmVjdGVkKHN0cnVjdCBkcm1faTkxNV9w cml2YXRlICpkZXZfcHJpdiwKPiA+PiAtCQkJCSAgICAgICBzdHJ1Y3QgaW50ZWxfZGlnaXRhbF9w b3J0ICpwb3J0KQo+ID4+ICtzdGF0aWMgYm9vbCBnbTQ1X2RpZ2l0YWxfcG9ydF9jb25uZWN0ZWQo c3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LAo+ID4+ICsJCQkJCXN0cnVjdCBpbnRl bF9kaWdpdGFsX3BvcnQgKnBvcnQpCj4gPj4gIHsKPiA+PiAgCXUzMiBiaXQ7Cj4gPj4gIAo+ID4+ ICAJc3dpdGNoIChwb3J0LT5wb3J0KSB7Cj4gPj4gIAljYXNlIFBPUlRfQjoKPiA+PiAtCQliaXQg PSBQT1JUQl9IT1RQTFVHX0xJVkVfU1RBVFVTX1ZMVjsKPiA+PiArCQliaXQgPSBQT1JUQl9IT1RQ TFVHX0xJVkVfU1RBVFVTX0dNNDU7Cj4gPj4gIAkJYnJlYWs7Cj4gPj4gIAljYXNlIFBPUlRfQzoK PiA+PiAtCQliaXQgPSBQT1JUQ19IT1RQTFVHX0xJVkVfU1RBVFVTX1ZMVjsKPiA+PiArCQliaXQg PSBQT1JUQ19IT1RQTFVHX0xJVkVfU1RBVFVTX0dNNDU7Cj4gPj4gIAkJYnJlYWs7Cj4gPj4gIAlj YXNlIFBPUlRfRDoKPiA+PiAtCQliaXQgPSBQT1JURF9IT1RQTFVHX0xJVkVfU1RBVFVTX1ZMVjsK PiA+PiArCQliaXQgPSBQT1JURF9IT1RQTFVHX0xJVkVfU1RBVFVTX0dNNDU7Cj4gPj4gIAkJYnJl YWs7Cj4gPj4gIAlkZWZhdWx0Ogo+ID4+ICAJCU1JU1NJTkdfQ0FTRShwb3J0LT5wb3J0KTsKPiA+ PiBAQCAtNDU1NSw4ICs0NTU1LDggQEAgYm9vbCBpbnRlbF9kaWdpdGFsX3BvcnRfY29ubmVjdGVk KHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwKPiA+PiAgCQlyZXR1cm4gY3B0X2Rp Z2l0YWxfcG9ydF9jb25uZWN0ZWQoZGV2X3ByaXYsIHBvcnQpOwo+ID4+ICAJZWxzZSBpZiAoSVNf QlJPWFRPTihkZXZfcHJpdikpCj4gPj4gIAkJcmV0dXJuIGJ4dF9kaWdpdGFsX3BvcnRfY29ubmVj dGVkKGRldl9wcml2LCBwb3J0KTsKPiA+PiAtCWVsc2UgaWYgKElTX1ZBTExFWVZJRVcoZGV2X3By aXYpIHx8IElTX0NIRVJSWVZJRVcoZGV2X3ByaXYpKQo+ID4+IC0JCXJldHVybiB2bHZfZGlnaXRh bF9wb3J0X2Nvbm5lY3RlZChkZXZfcHJpdiwgcG9ydCk7Cj4gPj4gKwllbHNlIGlmIChJU19HTTQ1 KGRldl9wcml2KSkKPiA+PiArCQlyZXR1cm4gZ200NV9kaWdpdGFsX3BvcnRfY29ubmVjdGVkKGRl dl9wcml2LCBwb3J0KTsKPiA+PiAgCWVsc2UKPiA+PiAgCQlyZXR1cm4gZzR4X2RpZ2l0YWxfcG9y dF9jb25uZWN0ZWQoZGV2X3ByaXYsIHBvcnQpOwo+ID4+ICB9Cj4gPj4gLS0gCj4gPj4gMi40LjEw Cj4gPj4gCj4gCj4gLS0gCj4gSmFuaSBOaWt1bGEsIEludGVsIE9wZW4gU291cmNlIFRlY2hub2xv Z3kgQ2VudGVyCgotLSAKVmlsbGUgU3lyasOkbMOkCkludGVsIE9UQwpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0Cklu dGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5v cmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com ([134.134.136.65]:17999 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753737AbcBORNz (ORCPT ); Mon, 15 Feb 2016 12:13:55 -0500 Date: Mon, 15 Feb 2016 19:13:51 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, Shashank Sharma , Sonika Jindal , Daniel Vetter , Nick Bowler , stable@vger.kernel.org Subject: Re: [PATCH] drm/i915: Fix hpd live status bits for g4x Message-ID: <20160215171351.GX23290@intel.com> References: <1455127145-20087-1-git-send-email-ville.syrjala@linux.intel.com> <20160211100358.GR11240@phenom.ffwll.local> <87vb5uqwa4.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87vb5uqwa4.fsf@intel.com> Sender: stable-owner@vger.kernel.org List-ID: On Fri, Feb 12, 2016 at 08:26:27AM +0200, Jani Nikula wrote: > On Thu, 11 Feb 2016, Daniel Vetter wrote: > > On Wed, Feb 10, 2016 at 07:59:05PM +0200, ville.syrjala@linux.intel.com wrote: > >> From: Ville Syrj�l� > >> > >> Looks like g4x hpd live status bits actually agree with the spec. At > >> least they do on the machine I have, and apparently on Nick Bowler's > >> g4x as well. > >> > >> So gm45 may be the only platform where they don't agree. At least > >> that seems to be the case based on the (somewhat incomplete) > >> logs/dumps in [1], and Daniel has also tested this on his gm45 > >> sometime in the past. > >> > >> So let's change the bits to match the spec on g4x. That actually makes > >> the g4x bits identical to vlv/chv so we can just share the code > >> between those platforms, leaving gm45 as the special case. > >> > >> [1] https://bugzilla.kernel.org/show_bug.cgi?id=52361 > >> > >> Cc: Shashank Sharma > >> Cc: Sonika Jindal > >> Cc: Daniel Vetter > >> Cc: Jani Nikula > >> Cc: Nick Bowler > >> References: https://lists.freedesktop.org/archives/dri-devel/2016-February/100382.html > >> Reported-by: Nick Bowler > >> Cc: stable@vger.kernel.org > >> Fixes: 237ed86c693d ("drm/i915: Check live status before reading edid") > >> Signed-off-by: Ville Syrj�l� > > > > Yeah I'm hopeful this will work. Reviewed-by: Daniel Vetter > > > > Since CI is down and this is super restricted impact and fixing a > > regression I'm voting that we'll pick it up right away. Jani, are you ok > > with that? > > Ack. "Right away" was slightly dealyed by my lazyness. Anyway, pushed this to dinq. Thanks for the review. > > > -Daniel > > > >> --- > >> drivers/gpu/drm/i915/i915_reg.h | 15 ++++++++------- > >> drivers/gpu/drm/i915/intel_dp.c | 14 +++++++------- > >> 2 files changed, 15 insertions(+), 14 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >> index 188ad5de020f..678faa957e75 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -3296,19 +3296,20 @@ enum skl_disp_power_wells { > >> > >> #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) > >> /* > >> - * HDMI/DP bits are gen4+ > >> + * HDMI/DP bits are g4x+ > >> * > >> * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. > >> * Please check the detailed lore in the commit message for for experimental > >> * evidence. > >> */ > >> -#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) > >> +/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ > >> +#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) > >> +#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) > >> +#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) > >> +/* G4X/VLV/CHV DP/HDMI bits again match Bspec */ > >> +#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) > >> #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) > >> -#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) > >> -/* VLV DP/HDMI bits again match Bspec */ > >> -#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) > >> -#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) > >> -#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) > >> +#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) > >> #define PORTD_HOTPLUG_INT_STATUS (3 << 21) > >> #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) > >> #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) > >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > >> index a073f04a5330..bbe18996efe6 100644 > >> --- a/drivers/gpu/drm/i915/intel_dp.c > >> +++ b/drivers/gpu/drm/i915/intel_dp.c > >> @@ -4490,20 +4490,20 @@ static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, > >> return I915_READ(PORT_HOTPLUG_STAT) & bit; > >> } > >> > >> -static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv, > >> - struct intel_digital_port *port) > >> +static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, > >> + struct intel_digital_port *port) > >> { > >> u32 bit; > >> > >> switch (port->port) { > >> case PORT_B: > >> - bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; > >> + bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; > >> break; > >> case PORT_C: > >> - bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; > >> + bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; > >> break; > >> case PORT_D: > >> - bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; > >> + bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; > >> break; > >> default: > >> MISSING_CASE(port->port); > >> @@ -4555,8 +4555,8 @@ bool intel_digital_port_connected(struct drm_i915_private *dev_priv, > >> return cpt_digital_port_connected(dev_priv, port); > >> else if (IS_BROXTON(dev_priv)) > >> return bxt_digital_port_connected(dev_priv, port); > >> - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > >> - return vlv_digital_port_connected(dev_priv, port); > >> + else if (IS_GM45(dev_priv)) > >> + return gm45_digital_port_connected(dev_priv, port); > >> else > >> return g4x_digital_port_connected(dev_priv, port); > >> } > >> -- > >> 2.4.10 > >> > > -- > Jani Nikula, Intel Open Source Technology Center -- Ville Syrj�l� Intel OTC