diff for duplicates of <20160223184513.GI19169@lukather> diff --git a/a/1.txt b/N1/1.txt index 3866e69..9a82acb 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -54,7 +54,7 @@ patch this node. > >> + clock-output-names = "osc32k"; > >> + }; > >> + -> >> + pll1: clk at 01c20000 { +> >> + pll1: clk@01c20000 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun8i-a23-pll1-clk"; > >> + reg = <0x01c20000 0x4>; @@ -62,7 +62,7 @@ patch this node. > >> + clock-output-names = "pll1"; > >> + }; > >> + -> >> + pll6: clk at 01c20028 { +> >> + pll6: clk@01c20028 { > >> + #clock-cells = <1>; > >> + compatible = "allwinner,sun6i-a31-pll6-clk"; > >> + reg = <0x01c20028 0x4>; @@ -97,7 +97,7 @@ Yeah. > >> + clock-output-names = "pll8"; > >> + }; > >> + -> >> + cpu: cpu_clk at 01c20050 { +> >> + cpu: cpu_clk@01c20050 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun4i-a10-cpu-clk"; > >> + reg = <0x01c20050 0x4>; @@ -106,7 +106,7 @@ Yeah. > >> + critical-clocks = <0>; > >> + }; > >> + -> >> + axi: axi_clk at 01c20050 { +> >> + axi: axi_clk@01c20050 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun4i-a10-axi-clk"; > >> + reg = <0x01c20050 0x4>; @@ -114,7 +114,7 @@ Yeah. > >> + clock-output-names = "axi"; > >> + }; > >> + -> >> + ahb1: ahb1_clk at 01c20054 { +> >> + ahb1: ahb1_clk@01c20054 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun6i-a31-ahb1-clk"; > >> + reg = <0x01c20054 0x4>; @@ -122,7 +122,7 @@ Yeah. > >> + clock-output-names = "ahb1"; > >> + }; > >> + -> >> + ahb2: ahb2_clk at 01c2005c { +> >> + ahb2: ahb2_clk@01c2005c { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun8i-h3-ahb2-clk"; > >> + reg = <0x01c2005c 0x4>; @@ -130,7 +130,7 @@ Yeah. > >> + clock-output-names = "ahb2"; > >> + }; > >> + -> >> + apb1: apb1_clk at 01c20054 { +> >> + apb1: apb1_clk@01c20054 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun4i-a10-apb0-clk"; > >> + reg = <0x01c20054 0x4>; @@ -138,7 +138,7 @@ Yeah. > >> + clock-output-names = "apb1"; > >> + }; > >> + -> >> + apb2: apb2_clk at 01c20058 { +> >> + apb2: apb2_clk@01c20058 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun4i-a10-apb1-clk"; > >> + reg = <0x01c20058 0x4>; @@ -146,7 +146,7 @@ Yeah. > >> + clock-output-names = "apb2"; > >> + }; > >> + -> >> + bus_gates: clk at 01c20060 { +> >> + bus_gates: clk@01c20060 { > >> + #clock-cells = <1>; > >> + compatible = "allwinner,a64-bus-gates-clk", > >> + "allwinner,sunxi-multi-bus-gates-clk"; @@ -353,7 +353,7 @@ have to switch to it in the future and break the ABI. Who would provide that firmware? The vendor? Whose binding were never ever reviewed? -> >> + pio: pinctrl at 01c20800 { +> >> + pio: pinctrl@01c20800 { > >> + compatible = "allwinner,a64-pinctrl"; > >> + reg = <0x01c20800 0x400>; > >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -365,42 +365,42 @@ ever reviewed? > >> + interrupt-controller; > >> + #interrupt-cells = <2>; > >> + -> >> + uart0_pins_a: uart0 at 0 { +> >> + uart0_pins_a: uart0@0 { > >> + allwinner,pins = "PB8", "PB9"; > >> + allwinner,function = "uart0"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart0_pins_b: uart0 at 1 { +> >> + uart0_pins_b: uart0@1 { > >> + allwinner,pins = "PF2", "PF3"; > >> + allwinner,function = "uart0"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart1_pins: uart1 at 0 { +> >> + uart1_pins: uart1@0 { > >> + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; > >> + allwinner,function = "uart1"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart2_pins: uart2 at 0 { +> >> + uart2_pins: uart2@0 { > >> + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; > >> + allwinner,function = "uart2"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart3_pins_a: uart3 at 0 { +> >> + uart3_pins_a: uart3@0 { > >> + allwinner,pins = "PD0", "PD1"; > >> + allwinner,function = "uart3"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart3_pins_b: uart3 at 1 { +> >> + uart3_pins_b: uart3@1 { > >> + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; > >> + allwinner,function = "uart3"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -429,10 +429,3 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: Digital signature -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160223/8cdfca44/attachment-0001.sig> diff --git a/a/content_digest b/N1/content_digest index 983218b..1754a8f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,11 +2,26 @@ "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" "ref\020160205085026.GA1139@lukather\0" "ref\056B8630B.8060608@arm.com\0" - "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" - "Subject\0[PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "ref\056B8630B.8060608-5wv7dgnIgG8@public.gmane.org\0" + "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Subject\0Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Tue, 23 Feb 2016 10:45:13 -0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>\0" + "Cc\0Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>" + linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org + Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "\01:1\0" "b\0" "Hi,\n" "\n" @@ -64,7 +79,7 @@ "> >> +\t\t\tclock-output-names = \"osc32k\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tpll1: clk at 01c20000 {\n" + "> >> +\t\tpll1: clk@01c20000 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> >> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -72,7 +87,7 @@ "> >> +\t\t\tclock-output-names = \"pll1\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tpll6: clk at 01c20028 {\n" + "> >> +\t\tpll6: clk@01c20028 {\n" "> >> +\t\t\t#clock-cells = <1>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> >> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -107,7 +122,7 @@ "> >> +\t\t\tclock-output-names = \"pll8\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> >> +\t\tcpu: cpu_clk@01c20050 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> >> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -116,7 +131,7 @@ "> >> +\t\t\tcritical-clocks = <0>;\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\taxi: axi_clk at 01c20050 {\n" + "> >> +\t\taxi: axi_clk@01c20050 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> >> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -124,7 +139,7 @@ "> >> +\t\t\tclock-output-names = \"axi\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> >> +\t\tahb1: ahb1_clk@01c20054 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> >> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -132,7 +147,7 @@ "> >> +\t\t\tclock-output-names = \"ahb1\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> >> +\t\tahb2: ahb2_clk@01c2005c {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> >> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -140,7 +155,7 @@ "> >> +\t\t\tclock-output-names = \"ahb2\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> >> +\t\tapb1: apb1_clk@01c20054 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> >> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -148,7 +163,7 @@ "> >> +\t\t\tclock-output-names = \"apb1\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> >> +\t\tapb2: apb2_clk@01c20058 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> >> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -156,7 +171,7 @@ "> >> +\t\t\tclock-output-names = \"apb2\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tbus_gates: clk at 01c20060 {\n" + "> >> +\t\tbus_gates: clk@01c20060 {\n" "> >> +\t\t\t#clock-cells = <1>;\n" "> >> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" "> >> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -363,7 +378,7 @@ "Who would provide that firmware? The vendor? Whose binding were never\n" "ever reviewed?\n" "\n" - "> >> +\t\tpio: pinctrl at 01c20800 {\n" + "> >> +\t\tpio: pinctrl@01c20800 {\n" "> >> +\t\t\tcompatible = \"allwinner,a64-pinctrl\";\n" "> >> +\t\t\treg = <0x01c20800 0x400>;\n" "> >> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -375,42 +390,42 @@ "> >> +\t\t\tinterrupt-controller;\n" "> >> +\t\t\t#interrupt-cells = <2>;\n" "> >> +\n" - "> >> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> >> +\t\t\tuart0_pins_a: uart0@0 {\n" "> >> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" "> >> +\t\t\t\tallwinner,function = \"uart0\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + "> >> +\t\t\tuart0_pins_b: uart0@1 {\n" "> >> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" "> >> +\t\t\t\tallwinner,function = \"uart0\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart1_pins: uart1 at 0 {\n" + "> >> +\t\t\tuart1_pins: uart1@0 {\n" "> >> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" "> >> +\t\t\t\tallwinner,function = \"uart1\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart2_pins: uart2 at 0 {\n" + "> >> +\t\t\tuart2_pins: uart2@0 {\n" "> >> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" "> >> +\t\t\t\tallwinner,function = \"uart2\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + "> >> +\t\t\tuart3_pins_a: uart3@0 {\n" "> >> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" "> >> +\t\t\t\tallwinner,function = \"uart3\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart3_pins_b: uart3 at 1 {\n" + "> >> +\t\t\tuart3_pins_b: uart3@1 {\n" "> >> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" "> >> +\t\t\t\tallwinner,function = \"uart3\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -438,13 +453,6 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: Digital signature\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160223/8cdfca44/attachment-0001.sig> + http://free-electrons.com -8437d9892b4bdb221a9fde2a3f9e49e95853e94d7309dbf51301a90a030bc6d1 +59e3d774047c480dd7234789120e417bdc3f855b1814118526bc08da60f7c562
diff --git a/a/1.txt b/N2/1.txt index 3866e69..9a82acb 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -54,7 +54,7 @@ patch this node. > >> + clock-output-names = "osc32k"; > >> + }; > >> + -> >> + pll1: clk at 01c20000 { +> >> + pll1: clk@01c20000 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun8i-a23-pll1-clk"; > >> + reg = <0x01c20000 0x4>; @@ -62,7 +62,7 @@ patch this node. > >> + clock-output-names = "pll1"; > >> + }; > >> + -> >> + pll6: clk at 01c20028 { +> >> + pll6: clk@01c20028 { > >> + #clock-cells = <1>; > >> + compatible = "allwinner,sun6i-a31-pll6-clk"; > >> + reg = <0x01c20028 0x4>; @@ -97,7 +97,7 @@ Yeah. > >> + clock-output-names = "pll8"; > >> + }; > >> + -> >> + cpu: cpu_clk at 01c20050 { +> >> + cpu: cpu_clk@01c20050 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun4i-a10-cpu-clk"; > >> + reg = <0x01c20050 0x4>; @@ -106,7 +106,7 @@ Yeah. > >> + critical-clocks = <0>; > >> + }; > >> + -> >> + axi: axi_clk at 01c20050 { +> >> + axi: axi_clk@01c20050 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun4i-a10-axi-clk"; > >> + reg = <0x01c20050 0x4>; @@ -114,7 +114,7 @@ Yeah. > >> + clock-output-names = "axi"; > >> + }; > >> + -> >> + ahb1: ahb1_clk at 01c20054 { +> >> + ahb1: ahb1_clk@01c20054 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun6i-a31-ahb1-clk"; > >> + reg = <0x01c20054 0x4>; @@ -122,7 +122,7 @@ Yeah. > >> + clock-output-names = "ahb1"; > >> + }; > >> + -> >> + ahb2: ahb2_clk at 01c2005c { +> >> + ahb2: ahb2_clk@01c2005c { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun8i-h3-ahb2-clk"; > >> + reg = <0x01c2005c 0x4>; @@ -130,7 +130,7 @@ Yeah. > >> + clock-output-names = "ahb2"; > >> + }; > >> + -> >> + apb1: apb1_clk at 01c20054 { +> >> + apb1: apb1_clk@01c20054 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun4i-a10-apb0-clk"; > >> + reg = <0x01c20054 0x4>; @@ -138,7 +138,7 @@ Yeah. > >> + clock-output-names = "apb1"; > >> + }; > >> + -> >> + apb2: apb2_clk at 01c20058 { +> >> + apb2: apb2_clk@01c20058 { > >> + #clock-cells = <0>; > >> + compatible = "allwinner,sun4i-a10-apb1-clk"; > >> + reg = <0x01c20058 0x4>; @@ -146,7 +146,7 @@ Yeah. > >> + clock-output-names = "apb2"; > >> + }; > >> + -> >> + bus_gates: clk at 01c20060 { +> >> + bus_gates: clk@01c20060 { > >> + #clock-cells = <1>; > >> + compatible = "allwinner,a64-bus-gates-clk", > >> + "allwinner,sunxi-multi-bus-gates-clk"; @@ -353,7 +353,7 @@ have to switch to it in the future and break the ABI. Who would provide that firmware? The vendor? Whose binding were never ever reviewed? -> >> + pio: pinctrl at 01c20800 { +> >> + pio: pinctrl@01c20800 { > >> + compatible = "allwinner,a64-pinctrl"; > >> + reg = <0x01c20800 0x400>; > >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -365,42 +365,42 @@ ever reviewed? > >> + interrupt-controller; > >> + #interrupt-cells = <2>; > >> + -> >> + uart0_pins_a: uart0 at 0 { +> >> + uart0_pins_a: uart0@0 { > >> + allwinner,pins = "PB8", "PB9"; > >> + allwinner,function = "uart0"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart0_pins_b: uart0 at 1 { +> >> + uart0_pins_b: uart0@1 { > >> + allwinner,pins = "PF2", "PF3"; > >> + allwinner,function = "uart0"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart1_pins: uart1 at 0 { +> >> + uart1_pins: uart1@0 { > >> + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; > >> + allwinner,function = "uart1"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart2_pins: uart2 at 0 { +> >> + uart2_pins: uart2@0 { > >> + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; > >> + allwinner,function = "uart2"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart3_pins_a: uart3 at 0 { +> >> + uart3_pins_a: uart3@0 { > >> + allwinner,pins = "PD0", "PD1"; > >> + allwinner,function = "uart3"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + -> >> + uart3_pins_b: uart3 at 1 { +> >> + uart3_pins_b: uart3@1 { > >> + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; > >> + allwinner,function = "uart3"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -429,10 +429,3 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: Digital signature -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160223/8cdfca44/attachment-0001.sig> diff --git a/N2/2.bin b/N2/2.bin new file mode 100644 index 0000000..eb94caa --- /dev/null +++ b/N2/2.bin @@ -0,0 +1,17 @@ +-----BEGIN PGP SIGNATURE----- +Version: GnuPG v1 + +iQIcBAEBAgAGBQJWzKi5AAoJEBx+YmzsjxAgmroP+gPhErMjEJAVM7+5gbeVjAry +4FxC1xJlxyPf1Q0/gd9EyhzrWNEHNSxbQa3LIcdNYwTpPgFZNL5gVGo60nv0SUMp +cbZLwHwtajAPgbGOlPlNQycDV+GniweeV+2ztFUwSJG8lDA02Aadv08SLkb5CGJi +UIVNUxbfKmPdB3QlIxPa/Vo/nL67t+utwhhCGSD+ikFm0Haj5vrd/+CqsvLU2tP9 +soK/MznfDD6wb5rDnSE3MTUO3fpIAjgSQ7xy5jXB6SiUKuAn4P+TU1Ih2DnISlsH +r6hyBTg9c7njBnUOFkgdPUyJVJ2WmbQlhFz4MGKKA+tA1LaavxKOYByUbImdH4Dg +xg7AtSj5LTvpfJ/PPuKhe/HJmeYbw44+Dh4nrMpl4ZI2g2/U3tLZziOts/Z7edlU +4dH2lZVOfyzCF6edFjGLTaOjTluCDu51fv6ruJgOomlx6hMjwzSfy807Nd+Ol07O +x6TToB+VEdRLznpLskC1BYs/MecszbA15CotNDI4xPRSzLZ00McozDMaOY49b+aD +AErV9RKi6xLvxSdLKbicjtbVDYZ4j7yQeCU1oj0ywneBQyiDQnzEssTpgRoRhTom +/jF2Aye87lcxSX3GU4tgRifaSqEYiwWjR5AzpPB+widhau2wWB2AKZbEFykg8Hcz +2dE70SxjAM3rA3q0gNZs +=kF6L +-----END PGP SIGNATURE----- diff --git a/N2/2.hdr b/N2/2.hdr new file mode 100644 index 0000000..3237378 --- /dev/null +++ b/N2/2.hdr @@ -0,0 +1,2 @@ +Content-Type: application/pgp-signature; name="signature.asc" +Content-Description: Digital signature diff --git a/a/content_digest b/N2/content_digest index 983218b..9f659fe 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,11 +2,25 @@ "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" "ref\020160205085026.GA1139@lukather\0" "ref\056B8630B.8060608@arm.com\0" - "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" - "Subject\0[PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "From\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" + "Subject\0Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Tue, 23 Feb 2016 10:45:13 -0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Andre Przywara <andre.przywara@arm.com>\0" + "Cc\0Chen-Yu Tsai <wens@csie.org>" + linux-sunxi@googlegroups.com + Arnd Bergmann <arnd@arndb.de> + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + Rob Herring <robh+dt@kernel.org> + Pawel Moll <pawel.moll@arm.com> + Mark Rutland <mark.rutland@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Kumar Gala <galak@codeaurora.org> + devicetree@vger.kernel.org + " Grant Likely <grant.likely@linaro.org>\0" + "\01:1\0" "b\0" "Hi,\n" "\n" @@ -64,7 +78,7 @@ "> >> +\t\t\tclock-output-names = \"osc32k\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tpll1: clk at 01c20000 {\n" + "> >> +\t\tpll1: clk@01c20000 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> >> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -72,7 +86,7 @@ "> >> +\t\t\tclock-output-names = \"pll1\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tpll6: clk at 01c20028 {\n" + "> >> +\t\tpll6: clk@01c20028 {\n" "> >> +\t\t\t#clock-cells = <1>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> >> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -107,7 +121,7 @@ "> >> +\t\t\tclock-output-names = \"pll8\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> >> +\t\tcpu: cpu_clk@01c20050 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> >> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -116,7 +130,7 @@ "> >> +\t\t\tcritical-clocks = <0>;\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\taxi: axi_clk at 01c20050 {\n" + "> >> +\t\taxi: axi_clk@01c20050 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> >> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -124,7 +138,7 @@ "> >> +\t\t\tclock-output-names = \"axi\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> >> +\t\tahb1: ahb1_clk@01c20054 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> >> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -132,7 +146,7 @@ "> >> +\t\t\tclock-output-names = \"ahb1\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> >> +\t\tahb2: ahb2_clk@01c2005c {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> >> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -140,7 +154,7 @@ "> >> +\t\t\tclock-output-names = \"ahb2\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> >> +\t\tapb1: apb1_clk@01c20054 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> >> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -148,7 +162,7 @@ "> >> +\t\t\tclock-output-names = \"apb1\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> >> +\t\tapb2: apb2_clk@01c20058 {\n" "> >> +\t\t\t#clock-cells = <0>;\n" "> >> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> >> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -156,7 +170,7 @@ "> >> +\t\t\tclock-output-names = \"apb2\";\n" "> >> +\t\t};\n" "> >> +\n" - "> >> +\t\tbus_gates: clk at 01c20060 {\n" + "> >> +\t\tbus_gates: clk@01c20060 {\n" "> >> +\t\t\t#clock-cells = <1>;\n" "> >> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" "> >> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -363,7 +377,7 @@ "Who would provide that firmware? The vendor? Whose binding were never\n" "ever reviewed?\n" "\n" - "> >> +\t\tpio: pinctrl at 01c20800 {\n" + "> >> +\t\tpio: pinctrl@01c20800 {\n" "> >> +\t\t\tcompatible = \"allwinner,a64-pinctrl\";\n" "> >> +\t\t\treg = <0x01c20800 0x400>;\n" "> >> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -375,42 +389,42 @@ "> >> +\t\t\tinterrupt-controller;\n" "> >> +\t\t\t#interrupt-cells = <2>;\n" "> >> +\n" - "> >> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> >> +\t\t\tuart0_pins_a: uart0@0 {\n" "> >> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" "> >> +\t\t\t\tallwinner,function = \"uart0\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + "> >> +\t\t\tuart0_pins_b: uart0@1 {\n" "> >> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" "> >> +\t\t\t\tallwinner,function = \"uart0\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart1_pins: uart1 at 0 {\n" + "> >> +\t\t\tuart1_pins: uart1@0 {\n" "> >> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" "> >> +\t\t\t\tallwinner,function = \"uart1\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart2_pins: uart2 at 0 {\n" + "> >> +\t\t\tuart2_pins: uart2@0 {\n" "> >> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" "> >> +\t\t\t\tallwinner,function = \"uart2\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + "> >> +\t\t\tuart3_pins_a: uart3@0 {\n" "> >> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" "> >> +\t\t\t\tallwinner,function = \"uart3\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> >> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> >> +\t\t\t};\n" "> >> +\n" - "> >> +\t\t\tuart3_pins_b: uart3 at 1 {\n" + "> >> +\t\t\tuart3_pins_b: uart3@1 {\n" "> >> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" "> >> +\t\t\t\tallwinner,function = \"uart3\";\n" "> >> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -438,13 +452,27 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: Digital signature\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160223/8cdfca44/attachment-0001.sig> + http://free-electrons.com + "\01:2\0" + "fn\0signature.asc\0" + "d\0Digital signature\0" + "b\0" + "-----BEGIN PGP SIGNATURE-----\n" + "Version: GnuPG v1\n" + "\n" + "iQIcBAEBAgAGBQJWzKi5AAoJEBx+YmzsjxAgmroP+gPhErMjEJAVM7+5gbeVjAry\n" + "4FxC1xJlxyPf1Q0/gd9EyhzrWNEHNSxbQa3LIcdNYwTpPgFZNL5gVGo60nv0SUMp\n" + "cbZLwHwtajAPgbGOlPlNQycDV+GniweeV+2ztFUwSJG8lDA02Aadv08SLkb5CGJi\n" + "UIVNUxbfKmPdB3QlIxPa/Vo/nL67t+utwhhCGSD+ikFm0Haj5vrd/+CqsvLU2tP9\n" + "soK/MznfDD6wb5rDnSE3MTUO3fpIAjgSQ7xy5jXB6SiUKuAn4P+TU1Ih2DnISlsH\n" + "r6hyBTg9c7njBnUOFkgdPUyJVJ2WmbQlhFz4MGKKA+tA1LaavxKOYByUbImdH4Dg\n" + "xg7AtSj5LTvpfJ/PPuKhe/HJmeYbw44+Dh4nrMpl4ZI2g2/U3tLZziOts/Z7edlU\n" + "4dH2lZVOfyzCF6edFjGLTaOjTluCDu51fv6ruJgOomlx6hMjwzSfy807Nd+Ol07O\n" + "x6TToB+VEdRLznpLskC1BYs/MecszbA15CotNDI4xPRSzLZ00McozDMaOY49b+aD\n" + "AErV9RKi6xLvxSdLKbicjtbVDYZ4j7yQeCU1oj0ywneBQyiDQnzEssTpgRoRhTom\n" + "/jF2Aye87lcxSX3GU4tgRifaSqEYiwWjR5AzpPB+widhau2wWB2AKZbEFykg8Hcz\n" + "2dE70SxjAM3rA3q0gNZs\n" + "=kF6L\n" + "-----END PGP SIGNATURE-----\n" -8437d9892b4bdb221a9fde2a3f9e49e95853e94d7309dbf51301a90a030bc6d1 +12b39943441916159b1dca554e96922ab5b084f5b56664bfa397ac2df28f8704
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