From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
To: Will Deacon <will.deacon@arm.com>
Cc: ralf@linux-mips.org, tony.luck@intel.com, fenghua.yu@intel.com,
linux-arch@vger.kernel.org
Subject: Re: Fw: Getting an early start on C++ standards issues...
Date: Fri, 26 Feb 2016 13:33:46 -0800 [thread overview]
Message-ID: <20160226213346.GL3522@linux.vnet.ibm.com> (raw)
In-Reply-To: <20160226152238.GE29125@arm.com>
On Fri, Feb 26, 2016 at 03:22:38PM +0000, Will Deacon wrote:
> On Fri, Feb 26, 2016 at 06:50:57AM -0800, Paul E. McKenney wrote:
> > Hello!
>
> Hi Paul,
>
> > Do ARM, MIPS, and IA64 data/address/control dependencies apply to loads
> > and stores from vector instructions? The use case appears to be that the
> > dependency chain is headed by a normal load instruction, and a dependency
> > to a later vector load/store is desired.
> >
> > Any other weakly ordered architectures with vector instructions?
>
> We certainly have instructions that don't honour address dependencies,
> for example LDNP (load non-temporal pair), and these could be used by
> variants of memcpy. x86 has something similar with MOVNTDQA[1].
>
> It's highly likely that we'd consider similar relaxations for extensions
> to our vector instructions in future revisions of the ARM architecture,
> so I don't think we should generally rely on address dependencies
> providing order for vectorised code.
Thank you for the information, Will!
Thanx, Paul
> Will
>
> [1] http://www.felixcloutier.com/x86/MOVNTDQA.html
>
prev parent reply other threads:[~2016-02-26 21:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-26 14:50 Fw: Getting an early start on C++ standards issues Paul E. McKenney
2016-02-26 15:22 ` Will Deacon
2016-02-26 21:33 ` Paul E. McKenney [this message]
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