From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: [PATCH] ARM: dts: DRA7: change address-cells and size-cells Date: Mon, 29 Feb 2016 15:01:46 -0800 Message-ID: <20160229230146.GT13417@atomide.com> References: <1456308664-28308-1-git-send-email-lokeshvutla@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1456308664-28308-1-git-send-email-lokeshvutla-l0cyMroinI0@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Lokesh Vutla Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Tero Kristo , nm-l0cyMroinI0@public.gmane.org, Sekhar Nori List-Id: linux-omap@vger.kernel.org * Lokesh Vutla [160224 02:14]: > DRA7 SoC has the capability to support DDR memory upto 4GB. In order to > represent this in memory dt node, the address-cells and size cells > should be 2. So, changing the address-cells and size-cells to 2 and > updating the memory nodes accordingly. Applying into omap-for-v4.6/dt thanks. Tony -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: tony@atomide.com (Tony Lindgren) Date: Mon, 29 Feb 2016 15:01:46 -0800 Subject: [PATCH] ARM: dts: DRA7: change address-cells and size-cells In-Reply-To: <1456308664-28308-1-git-send-email-lokeshvutla@ti.com> References: <1456308664-28308-1-git-send-email-lokeshvutla@ti.com> Message-ID: <20160229230146.GT13417@atomide.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org * Lokesh Vutla [160224 02:14]: > DRA7 SoC has the capability to support DDR memory upto 4GB. In order to > represent this in memory dt node, the address-cells and size cells > should be 2. So, changing the address-cells and size-cells to 2 and > updating the memory nodes accordingly. Applying into omap-for-v4.6/dt thanks. Tony