From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1adjC4-0004EX-DP for linux-mtd@lists.infradead.org; Wed, 09 Mar 2016 18:50:48 +0000 Received: by mail-pf0-x22e.google.com with SMTP id 129so47619308pfw.1 for ; Wed, 09 Mar 2016 10:50:27 -0800 (PST) Date: Wed, 9 Mar 2016 10:50:24 -0800 From: Brian Norris To: Jiancheng Xue Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, dwmw2@infradead.org, zajec5@gmail.com, boris.brezillon@free-electrons.com, jteki@openedev.com, ezequiel@vanguardiasur.com.ar, juhosg@openwrt.org, shijie.huang@intel.com, mika.westerberg@linux.intel.com, furquan@google.com, han.xu@freescale.com, fabio.estevam@freescale.com, manabian@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, yanhaifeng@hisilicon.com, yanghongwei@hisilicon.com, suwenping@hisilicon.com, raojun@hisilicon.com, ml.yang@hisilicon.com, gaofei@hisilicon.com, zhangzhenxing@hisilicon.com, xuejiancheng@hisilicon.com, Binquan Peng Subject: Re: [RESEND PATCH v7] mtd: spi-nor: add hisilicon spi-nor flash controller driver Message-ID: <20160309185024.GN55664@google.com> References: <1456474316-24473-1-git-send-email-xuejiancheng@huawei.com> <20160307225229.GC55664@google.com> <56DE9A79.30704@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <56DE9A79.30704@huawei.com> List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, Mar 08, 2016 at 05:25:13PM +0800, Jiancheng Xue wrote: > On 2016/3/8 6:52, Brian Norris wrote: > [...] > >> +static void hisi_spi_nor_dma_transfer(struct spi_nor *nor, u32 start_off, > >> + u32 dma_buf, u32 len, u8 op_type) > > > > Does this controller support 64-bit addresses? What if you see LPAE, or > > an ARM64 CPU? It'd be nice if you don't truncate potentially 64-bit > > dma_buf down to u32. > > > > Brian > > > No, this controller just supports 32-bit addresses. So I think I have to truncate 64-bit dma_buf. :( Then you should handle this proactively. Either some kind of WARN_ON and error condition, or I think dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) should be able to ensure you get addresses in the appropriate range? Brian From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brian Norris Subject: Re: [RESEND PATCH v7] mtd: spi-nor: add hisilicon spi-nor flash controller driver Date: Wed, 9 Mar 2016 10:50:24 -0800 Message-ID: <20160309185024.GN55664@google.com> References: <1456474316-24473-1-git-send-email-xuejiancheng@huawei.com> <20160307225229.GC55664@google.com> <56DE9A79.30704@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <56DE9A79.30704-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Jiancheng Xue Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, jteki-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org, ezequiel-30ULvvUtt6G51wMPkGsGjgyUoB5FGQPZ@public.gmane.org, juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org, shijie.huang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org, furquan-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, han.xu-KZfg59tc24xl57MIdRCFDg@public.gmane.org, fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org, manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, yanhaifeng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, yanghongwei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, suwenping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, raojun-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, ml.yang-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, gaofei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, zhangzhenxing-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, Binquan Peng List-Id: devicetree@vger.kernel.org On Tue, Mar 08, 2016 at 05:25:13PM +0800, Jiancheng Xue wrote: > On 2016/3/8 6:52, Brian Norris wrote: > [...] > >> +static void hisi_spi_nor_dma_transfer(struct spi_nor *nor, u32 start_off, > >> + u32 dma_buf, u32 len, u8 op_type) > > > > Does this controller support 64-bit addresses? What if you see LPAE, or > > an ARM64 CPU? It'd be nice if you don't truncate potentially 64-bit > > dma_buf down to u32. > > > > Brian > > > No, this controller just supports 32-bit addresses. So I think I have to truncate 64-bit dma_buf. :( Then you should handle this proactively. Either some kind of WARN_ON and error condition, or I think dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) should be able to ensure you get addresses in the appropriate range? Brian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html