From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2] drm/i915: Exit cherryview_irq_handler() after one pass Date: Thu, 10 Mar 2016 14:25:11 +0200 Message-ID: <20160310122511.GG10446@intel.com> References: <1457610268-25299-1-git-send-email-chris@chris-wilson.co.uk> <1457612329-21632-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 474FA6E95D for ; Thu, 10 Mar 2016 12:25:15 +0000 (UTC) Content-Disposition: inline In-Reply-To: <1457612329-21632-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org, Antti =?iso-8859-1?Q?Koskip=E4=E4?= , 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Mar 2016 07:25:16 -0500 Date: Thu, 10 Mar 2016 14:25:11 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org, Antti =?iso-8859-1?Q?Koskip=E4=E4?= , Tvrtko Ursulin , stable@vger.kernel.org Subject: Re: [PATCH v2] drm/i915: Exit cherryview_irq_handler() after one pass Message-ID: <20160310122511.GG10446@intel.com> References: <1457610268-25299-1-git-send-email-chris@chris-wilson.co.uk> <1457612329-21632-1-git-send-email-chris@chris-wilson.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1457612329-21632-1-git-send-email-chris@chris-wilson.co.uk> Sender: stable-owner@vger.kernel.org List-ID: On Thu, Mar 10, 2016 at 12:18:49PM +0000, Chris Wilson wrote: > This effectively reverts > > commit 8e5fd599eb219f1054e39b40d18b217af669eea9 > Author: Ville Syrj�l� > Date: Wed Apr 9 13:28:50 2014 +0300 > > drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed > > as under continuous execlists load we can saturate the IRQ handler, > destablising the tsc clock and triggering the NMI watchdog to declare a hung > CPU. > > [ 552.756051] clocksource: timekeeping watchdog on CPU0: Marking clocksource 'tsc' as unstable because the skew is too large: > [ 552.756080] clocksource: 'refined-jiffies' wd_now: 10003b480 wd_last: 10003b28c mask: ffffffff > [ 552.756091] clocksource: 'tsc' cs_now: d55d31aa50 cs_last: d17446166c mask: ffffffffffffffff > [ 552.756210] clocksource: Switched to clocksource refined-jiffies > [ 575.217870] NMI watchdog: Watchdog detected hard LOCKUP on cpu 1 > [ 575.217893] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.5.0-rc7+ #18 > [ 575.217905] Hardware name: /NUC5CPYB, BIOS PYBSWCEL.86A.0027.2015.0507.1758 05/07/2015 > [ 575.217915] 0000000000000000 ffff88027fd05bc0 ffffffff81288c6d 0000000000000000 > [ 575.217935] 0000000000000001 ffff88027fd05be0 ffffffff810e72d1 0000000000000000 > [ 575.217951] ffff88027fd05c80 ffff88027fd05c20 ffffffff81114b60 0000000181015f1e > [ 575.217967] Call Trace: > [ 575.217973] [] dump_stack+0x4f/0x72 > [ 575.217994] [] watchdog_overflow_callback+0x151/0x160 > [ 575.218003] [] __perf_event_overflow+0xa0/0x1e0 > [ 575.218016] [] perf_event_overflow+0x14/0x20 > [ 575.218028] [] intel_pmu_handle_irq+0x1da/0x460 > [ 575.218042] [] ? poll_idle+0x3e/0x70 > [ 575.218052] [] ? poll_idle+0x3e/0x70 > [ 575.218064] [] perf_event_nmi_handler+0x28/0x50 > [ 575.218075] [] nmi_handle+0x60/0x130 > [ 575.218086] [] ? poll_idle+0x3e/0x70 > [ 575.218096] [] do_nmi+0x140/0x470 > [ 575.218108] [] end_repeat_nmi+0x1a/0x1e > [ 575.218119] [] ? poll_idle+0x3e/0x70 > [ 575.218129] [] ? poll_idle+0x3e/0x70 > [ 575.218139] [] ? poll_idle+0x3e/0x70 > [ 575.218148] <> [] cpuidle_enter_state+0xf3/0x2f0 > [ 575.218164] [] cpuidle_enter+0x17/0x20 > [ 575.218175] [] call_cpuidle+0x2a/0x40 > [ 575.218185] [] cpu_startup_entry+0x273/0x330 > [ 575.218196] [] start_secondary+0x10e/0x130 > > However, not servicing all available IIR within the handler does hurt the > throughput of pathological nop execbuf by about 20%, with a similar effect > upon the dispatch latency of a series of execbuf. > > v2: use do {} while(0) for a smaller patch, and easier to revert again > > We have reasonable confidence that we do not miss GT interrupts (as > execlists provides a stress case with a failure mechanism easily > detected by igt), however we have less confidence about all the other > sources of interrupts and worry that may lose a display hotplug > interrupt, for example. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93467 > Testcase: igt/gem_exec_nop/basic # requires NMI watchdog > Signed-off-by: Chris Wilson > Cc: Ville Syrj�l� > Cc: Antti Koskip�� Cc: Tvrtko Ursulin > Cc: stable@vger.kernel.org > Acked-by: Tvrtko Ursulin Acked-by: Ville Syrj�l� > --- > drivers/gpu/drm/i915/i915_irq.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 53e5104964b3..30d8bb7bf078 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1829,7 +1829,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) > /* IRQs are synced during runtime_suspend, we don't require a wakeref */ > disable_rpm_wakeref_asserts(dev_priv); > > - for (;;) { > + do { > master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; > iir = I915_READ(VLV_IIR); > > @@ -1857,7 +1857,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) > > I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); > POSTING_READ(GEN8_MASTER_IRQ); > - } > + } while (0); > > enable_rpm_wakeref_asserts(dev_priv); > > -- > 2.7.0 -- Ville Syrj�l� Intel OTC