Re: imx6ul uart modem lines and the device tree

[Oliver Graute <oliver.graute@gmail.com>]

On 10/03/16, Oliver Graute wrote:
> Hello,
> 
> I try to use the GPIO2_IO20 and the GPIO2_IO21 as GPIO pin for uart
> modem signals and not as PIN to the USDHC1 sdcard interface of the
> imx6ulevk.
> 
> if I write 5 direct to the MUX Ctrl Register
> 
> devmem2 0x020e01cc w 5
> devmem2 0x020e01d0 w 5
> 
> it works until next boot.
> 
> I assume that I have to change something in the device tree files of
> linux to reflect the HW gpio changes. How do I adjust the
> imx6ul-14x14-evk-csi.dts for this?

I tried without success the following modifications to my devicetree, But the

Mux Ctrl Register 0x020e01cc and 0x020e01d0 doesn't contain the value 5 :-(


Index: kernel-source/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts
===================================================================
--- kernel-source.orig/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts	2016-03-11 15:48:40.780584851 +0100
+++ kernel-source/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts	2016-03-15 18:01:41.686179509 +0100
@@ -362,8 +362,33 @@
 			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 		>;
 	};
+
+	pinctrl_gpio_key: gpio_keygrp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_DATA2__GPIO2_IO20          0x17059 /* enter the values of the pad config here*/
+			MX6UL_PAD_SD1_DATA3__GPIO2_IO21          0x17059 /* enter the values of the pad config here*/
+                        >;
+                };
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_key>;
+
+		DTR {
+			label = "DTR";
+			gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+		};
+
+		DCD {
+			label = "DCD";
+			gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
+		};
+
+	};
+
 };
 
 &i2c1 {
 	status = "okay";
 	pinctrl-names = "default";

Index: kernel-source/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts
===================================================================
--- kernel-source.orig/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts	2016-03-09 11:26:19.598366947 +0100
+++ kernel-source/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts	2016-03-09 11:34:30.544041844 +0100
@@ -124,17 +124,17 @@
 	status = "okay";
 };
 
-&usdhc1 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-	keep-power-in-suspend;
-	enable-sdio-wakeup;
-	vmmc-supply = <&reg_sd1_vmmc>;
-	status = "okay";
-};
+//&usdhc1 {
+//	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+//	pinctrl-0 = <&pinctrl_usdhc1>;
+//	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+//	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+//	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+//	keep-power-in-suspend;
+//	enable-sdio-wakeup;
+//	vmmc-supply = <&reg_sd1_vmmc>;
+//	status = "okay";
+//};
 
 &usdhc2 {
 	pinctrl-names = "default";
@@ -312,23 +312,25 @@
 			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
 			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
 			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
 			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
 			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
-			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
-			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
-			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 		>;
 	};
 
+//	pinctrl_usdhc1: usdhc1grp {
+//		fsl,pins = <
+//			MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
+//			MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
+//			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
+//			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
+//			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
+//			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
+//			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
+//			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
+//			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+//		>;
+//	};
+
 	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9

Best Regards,

Oliver