From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/2] drm/i915: Get rid of intel_dp_dpcd_read_wake() Date: Fri, 18 Mar 2016 16:13:45 +0200 Message-ID: <20160318141345.GG4329@intel.com> References: <1458229245-8634-1-git-send-email-cpaul@redhat.com> <1458229245-8634-2-git-send-email-cpaul@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1458229245-8634-2-git-send-email-cpaul@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Lyude Cc: David Airlie , intel-gfx@lists.freedesktop.org, arthur.j.runyan@intel.com, open list , dri-devel@lists.freedesktop.org, Daniel Vetter List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBNYXIgMTcsIDIwMTYgYXQgMTE6NDA6NDVBTSAtMDQwMCwgTHl1ZGUgd3JvdGU6Cj4g U2luY2Ugd2UndmUgZml4ZWQgdXAgZHJtX2RwX2RwY2RfcmVhZCgpIHRvIGFsbG93IGZvciByZXRy aWVzIHdoZW4gdGhpbmdzCj4gdGltZW91dCwgdGhlcmUncyBubyB1c2UgZm9yIGhhdmluZyB0aGlz IGZ1bmN0aW9uIGFueW1vcmUuIEdvb2QgcmlkZGVucy4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBMeXVk ZSA8Y3BhdWxAcmVkaGF0LmNvbT4KPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxf ZHAuYyB8IDc5ICsrKysrKysrKysrKy0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tCj4gIDEg ZmlsZSBjaGFuZ2VkLCAyMiBpbnNlcnRpb25zKCspLCA1NyBkZWxldGlvbnMoLSkKPiAKPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHAuYyBiL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2ludGVsX2RwLmMKPiBpbmRleCBjZGMyYzE1Li5mYjRjYmJlNSAxMDA2NDQKPiAtLS0g YS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcC5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJt L2k5MTUvaW50ZWxfZHAuYwo+IEBAIC0zMTkwLDQ3ICszMTkwLDE0IEBAIHN0YXRpYyB2b2lkIGNo dl9kcF9wb3N0X3BsbF9kaXNhYmxlKHN0cnVjdCBpbnRlbF9lbmNvZGVyICplbmNvZGVyKQo+ICB9 Cj4gIAo+ICAvKgo+IC0gKiBOYXRpdmUgcmVhZCB3aXRoIHJldHJ5IGZvciBsaW5rIHN0YXR1cyBh bmQgcmVjZWl2ZXIgY2FwYWJpbGl0eSByZWFkcyBmb3IKPiAtICogY2FzZXMgd2hlcmUgdGhlIHNp bmsgbWF5IHN0aWxsIGJlIGFzbGVlcC4KPiAtICoKPiAtICogU2lua3MgYXJlICpzdXBwb3NlZCog dG8gY29tZSB1cCB3aXRoaW4gMW1zIGZyb20gYW4gb2ZmIHN0YXRlLCBidXQgd2UncmUgYWxzbwo+ IC0gKiBzdXBwb3NlZCB0byByZXRyeSAzIHRpbWVzIHBlciB0aGUgc3BlYy4KPiAtICovCj4gLXN0 YXRpYyBzc2l6ZV90Cj4gLWludGVsX2RwX2RwY2RfcmVhZF93YWtlKHN0cnVjdCBkcm1fZHBfYXV4 ICphdXgsIHVuc2lnbmVkIGludCBvZmZzZXQsCj4gLQkJCXZvaWQgKmJ1ZmZlciwgc2l6ZV90IHNp emUpCj4gLXsKPiAtCXNzaXplX3QgcmV0Owo+IC0JaW50IGk7Cj4gLQo+IC0JLyoKPiAtCSAqIFNv bWV0aW1lIHdlIGp1c3QgZ2V0IHRoZSBzYW1lIGluY29ycmVjdCBieXRlIHJlcGVhdGVkCj4gLQkg KiBvdmVyIHRoZSBlbnRpcmUgYnVmZmVyLiBEb2luZyBqdXN0IG9uZSB0aHJvdyBhd2F5IHJlYWQK PiAtCSAqIGluaXRpYWxseSBzZWVtcyB0byAic29sdmUiIGl0Lgo+IC0JICovCj4gLQlkcm1fZHBf ZHBjZF9yZWFkKGF1eCwgRFBfRFBDRF9SRVYsIGJ1ZmZlciwgMSk7CgpOQUsKCklmIHBlb3BsZSBr ZWVwIGludGVudGlvbmFsbHkgYnJlYWtpbmcgbXkgc2hpdCBJJ20gZ29pbmcgdG8gYmVjb21lCnJl YWxseSBncnVtcHkgc29vbi4KCgo+IC0KPiAtCWZvciAoaSA9IDA7IGkgPCAzOyBpKyspIHsKPiAt CQlyZXQgPSBkcm1fZHBfZHBjZF9yZWFkKGF1eCwgb2Zmc2V0LCBidWZmZXIsIHNpemUpOwo+IC0J CWlmIChyZXQgPT0gc2l6ZSkKPiAtCQkJcmV0dXJuIHJldDsKPiAtCQltc2xlZXAoMSk7Cj4gLQl9 Cj4gLQo+IC0JcmV0dXJuIHJldDsKPiAtfQo+IC0KPiAtLyoKPiAgICogRmV0Y2ggQVVYIENIIHJl Z2lzdGVycyAweDIwMiAtIDB4MjA3IHdoaWNoIGNvbnRhaW4KPiAgICogbGluayBzdGF0dXMgaW5m b3JtYXRpb24KPiAgICovCj4gIGJvb2wKPiAgaW50ZWxfZHBfZ2V0X2xpbmtfc3RhdHVzKHN0cnVj dCBpbnRlbF9kcCAqaW50ZWxfZHAsIHVpbnQ4X3QgbGlua19zdGF0dXNbRFBfTElOS19TVEFUVVNf U0laRV0pCj4gIHsKPiAtCXJldHVybiBpbnRlbF9kcF9kcGNkX3JlYWRfd2FrZSgmaW50ZWxfZHAt PmF1eCwKPiAtCQkJCSAgICAgICBEUF9MQU5FMF8xX1NUQVRVUywKPiAtCQkJCSAgICAgICBsaW5r X3N0YXR1cywKPiAtCQkJCSAgICAgICBEUF9MSU5LX1NUQVRVU19TSVpFKSA9PSBEUF9MSU5LX1NU QVRVU19TSVpFOwo+ICsJcmV0dXJuIGRybV9kcF9kcGNkX3JlYWQoJmludGVsX2RwLT5hdXgsIERQ X0xBTkUwXzFfU1RBVFVTLCBsaW5rX3N0YXR1cywKPiArCQkJCURQX0xJTktfU1RBVFVTX1NJWkUp ID09IERQX0xJTktfU1RBVFVTX1NJWkU7Cj4gIH0KPiAgCj4gIC8qIFRoZXNlIGFyZSBzb3VyY2Ut c3BlY2lmaWMgdmFsdWVzLiAqLwo+IEBAIC0zODY1LDggKzM4MzIsOCBAQCBpbnRlbF9kcF9nZXRf ZHBjZChzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwKQo+ICAJc3RydWN0IGRybV9pOTE1X3ByaXZh dGUgKmRldl9wcml2ID0gZGV2LT5kZXZfcHJpdmF0ZTsKPiAgCXVpbnQ4X3QgcmV2Owo+ICAKPiAt CWlmIChpbnRlbF9kcF9kcGNkX3JlYWRfd2FrZSgmaW50ZWxfZHAtPmF1eCwgMHgwMDAsIGludGVs X2RwLT5kcGNkLAo+IC0JCQkJICAgIHNpemVvZihpbnRlbF9kcC0+ZHBjZCkpIDwgMCkKPiArCWlm IChkcm1fZHBfZHBjZF9yZWFkKCZpbnRlbF9kcC0+YXV4LCAweDAwMCwgaW50ZWxfZHAtPmRwY2Qs Cj4gKwkJCSAgICAgc2l6ZW9mKGludGVsX2RwLT5kcGNkKSkgPCAwKQo+ICAJCXJldHVybiBmYWxz ZTsgLyogYXV4IHRyYW5zZmVyIGZhaWxlZCAqLwo+ICAKPiAgCURSTV9ERUJVR19LTVMoIkRQQ0Q6 ICUqcGhcbiIsIChpbnQpIHNpemVvZihpbnRlbF9kcC0+ZHBjZCksIGludGVsX2RwLT5kcGNkKTsK PiBAQCAtMzg3Nyw5ICszODQ0LDkgQEAgaW50ZWxfZHBfZ2V0X2RwY2Qoc3RydWN0IGludGVsX2Rw ICppbnRlbF9kcCkKPiAgCS8qIENoZWNrIGlmIHRoZSBwYW5lbCBzdXBwb3J0cyBQU1IgKi8KPiAg CW1lbXNldChpbnRlbF9kcC0+cHNyX2RwY2QsIDAsIHNpemVvZihpbnRlbF9kcC0+cHNyX2RwY2Qp KTsKPiAgCWlmIChpc19lZHAoaW50ZWxfZHApKSB7Cj4gLQkJaW50ZWxfZHBfZHBjZF9yZWFkX3dh a2UoJmludGVsX2RwLT5hdXgsIERQX1BTUl9TVVBQT1JULAo+IC0JCQkJCWludGVsX2RwLT5wc3Jf ZHBjZCwKPiAtCQkJCQlzaXplb2YoaW50ZWxfZHAtPnBzcl9kcGNkKSk7Cj4gKwkJZHJtX2RwX2Rw Y2RfcmVhZCgmaW50ZWxfZHAtPmF1eCwgRFBfUFNSX1NVUFBPUlQsCj4gKwkJCQkgaW50ZWxfZHAt PnBzcl9kcGNkLAo+ICsJCQkJIHNpemVvZihpbnRlbF9kcC0+cHNyX2RwY2QpKTsKPiAgCQlpZiAo aW50ZWxfZHAtPnBzcl9kcGNkWzBdICYgRFBfUFNSX0lTX1NVUFBPUlRFRCkgewo+ICAJCQlkZXZf cHJpdi0+cHNyLnNpbmtfc3VwcG9ydCA9IHRydWU7Cj4gIAkJCURSTV9ERUJVR19LTVMoIkRldGVj dGVkIEVEUCBQU1IgUGFuZWwuXG4iKTsKPiBAQCAtMzg5MCw5ICszODU3LDkgQEAgaW50ZWxfZHBf Z2V0X2RwY2Qoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCkKPiAgCQkJdWludDhfdCBmcmFtZV9z eW5jX2NhcDsKPiAgCj4gIAkJCWRldl9wcml2LT5wc3Iuc2lua19zdXBwb3J0ID0gdHJ1ZTsKPiAt CQkJaW50ZWxfZHBfZHBjZF9yZWFkX3dha2UoJmludGVsX2RwLT5hdXgsCj4gLQkJCQkJRFBfU0lO S19ERVZJQ0VfQVVYX0ZSQU1FX1NZTkNfQ0FQLAo+IC0JCQkJCSZmcmFtZV9zeW5jX2NhcCwgMSk7 Cj4gKwkJCWRybV9kcF9kcGNkX3JlYWQoJmludGVsX2RwLT5hdXgsCj4gKwkJCQkJIERQX1NJTktf REVWSUNFX0FVWF9GUkFNRV9TWU5DX0NBUCwKPiArCQkJCQkgJmZyYW1lX3N5bmNfY2FwLCAxKTsK PiAgCQkJZGV2X3ByaXYtPnBzci5hdXhfZnJhbWVfc3luYyA9IGZyYW1lX3N5bmNfY2FwID8gdHJ1 ZSA6IGZhbHNlOwo+ICAJCQkvKiBQU1IyIG5lZWRzIGZyYW1lIHN5bmMgYXMgd2VsbCAqLwo+ICAJ CQlkZXZfcHJpdi0+cHNyLnBzcjJfc3VwcG9ydCA9IGRldl9wcml2LT5wc3IuYXV4X2ZyYW1lX3N5 bmM7Cj4gQEAgLTM5MDgsMTUgKzM4NzUsMTMgQEAgaW50ZWxfZHBfZ2V0X2RwY2Qoc3RydWN0IGlu dGVsX2RwICppbnRlbF9kcCkKPiAgCS8qIEludGVybWVkaWF0ZSBmcmVxdWVuY3kgc3VwcG9ydCAq Lwo+ICAJaWYgKGlzX2VkcChpbnRlbF9kcCkgJiYKPiAgCSAgICAoaW50ZWxfZHAtPmRwY2RbRFBf RURQX0NPTkZJR1VSQVRJT05fQ0FQXSAmCURQX0RQQ0RfRElTUExBWV9DT05UUk9MX0NBUEFCTEUp ICYmCj4gLQkgICAgKGludGVsX2RwX2RwY2RfcmVhZF93YWtlKCZpbnRlbF9kcC0+YXV4LCBEUF9F RFBfRFBDRF9SRVYsICZyZXYsIDEpID09IDEpICYmCj4gKwkgICAgKGRybV9kcF9kcGNkX3JlYWQo JmludGVsX2RwLT5hdXgsIERQX0VEUF9EUENEX1JFViwgJnJldiwgMSkgPT0gMSkgJiYKPiAgCSAg ICAocmV2ID49IDB4MDMpKSB7IC8qIGVEcCB2MS40IG9yIGhpZ2hlciAqLwo+ICAJCV9fbGUxNiBz aW5rX3JhdGVzW0RQX01BWF9TVVBQT1JURURfUkFURVNdOwo+ICAJCWludCBpOwo+ICAKPiAtCQlp bnRlbF9kcF9kcGNkX3JlYWRfd2FrZSgmaW50ZWxfZHAtPmF1eCwKPiAtCQkJCURQX1NVUFBPUlRF RF9MSU5LX1JBVEVTLAo+IC0JCQkJc2lua19yYXRlcywKPiAtCQkJCXNpemVvZihzaW5rX3JhdGVz KSk7Cj4gKwkJZHJtX2RwX2RwY2RfcmVhZCgmaW50ZWxfZHAtPmF1eCwgRFBfU1VQUE9SVEVEX0xJ TktfUkFURVMsCj4gKwkJCQlzaW5rX3JhdGVzLCBzaXplb2Yoc2lua19yYXRlcykpOwo+ICAKPiAg CQlmb3IgKGkgPSAwOyBpIDwgQVJSQVlfU0laRShzaW5rX3JhdGVzKTsgaSsrKSB7Cj4gIAkJCWlu dCB2YWwgPSBsZTE2X3RvX2NwdShzaW5rX3JhdGVzW2ldKTsKPiBAQCAtMzkzOSw5ICszOTA0LDkg QEAgaW50ZWxfZHBfZ2V0X2RwY2Qoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCkKPiAgCWlmIChp bnRlbF9kcC0+ZHBjZFtEUF9EUENEX1JFVl0gPT0gMHgxMCkKPiAgCQlyZXR1cm4gdHJ1ZTsgLyog bm8gcGVyLXBvcnQgZG93bnN0cmVhbSBpbmZvICovCj4gIAo+IC0JaWYgKGludGVsX2RwX2RwY2Rf cmVhZF93YWtlKCZpbnRlbF9kcC0+YXV4LCBEUF9ET1dOU1RSRUFNX1BPUlRfMCwKPiAtCQkJCSAg ICBpbnRlbF9kcC0+ZG93bnN0cmVhbV9wb3J0cywKPiAtCQkJCSAgICBEUF9NQVhfRE9XTlNUUkVB TV9QT1JUUykgPCAwKQo+ICsJaWYgKGRybV9kcF9kcGNkX3JlYWQoJmludGVsX2RwLT5hdXgsIERQ X0RPV05TVFJFQU1fUE9SVF8wLAo+ICsJCQkgICAgIGludGVsX2RwLT5kb3duc3RyZWFtX3BvcnRz LAo+ICsJCQkgICAgIERQX01BWF9ET1dOU1RSRUFNX1BPUlRTKSA8IDApCj4gIAkJcmV0dXJuIGZh bHNlOyAvKiBkb3duc3RyZWFtIHBvcnQgc3RhdHVzIGZldGNoIGZhaWxlZCAqLwo+ICAKPiAgCXJl dHVybiB0cnVlOwo+IEBAIC0zOTU1LDExICszOTIwLDExIEBAIGludGVsX2RwX3Byb2JlX291aShz dHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwKQo+ICAJaWYgKCEoaW50ZWxfZHAtPmRwY2RbRFBfRE9X Tl9TVFJFQU1fUE9SVF9DT1VOVF0gJiBEUF9PVUlfU1VQUE9SVCkpCj4gIAkJcmV0dXJuOwo+ICAK PiAtCWlmIChpbnRlbF9kcF9kcGNkX3JlYWRfd2FrZSgmaW50ZWxfZHAtPmF1eCwgRFBfU0lOS19P VUksIGJ1ZiwgMykgPT0gMykKPiArCWlmIChkcm1fZHBfZHBjZF9yZWFkKCZpbnRlbF9kcC0+YXV4 LCBEUF9TSU5LX09VSSwgYnVmLCAzKSA9PSAzKQo+ICAJCURSTV9ERUJVR19LTVMoIlNpbmsgT1VJ OiAlMDJoeCUwMmh4JTAyaHhcbiIsCj4gIAkJCSAgICAgIGJ1ZlswXSwgYnVmWzFdLCBidWZbMl0p Owo+ICAKPiAtCWlmIChpbnRlbF9kcF9kcGNkX3JlYWRfd2FrZSgmaW50ZWxfZHAtPmF1eCwgRFBf QlJBTkNIX09VSSwgYnVmLCAzKSA9PSAzKQo+ICsJaWYgKGRybV9kcF9kcGNkX3JlYWQoJmludGVs X2RwLT5hdXgsIERQX0JSQU5DSF9PVUksIGJ1ZiwgMykgPT0gMykKPiAgCQlEUk1fREVCVUdfS01T KCJCcmFuY2ggT1VJOiAlMDJoeCUwMmh4JTAyaHhcbiIsCj4gIAkJCSAgICAgIGJ1ZlswXSwgYnVm WzFdLCBidWZbMl0pOwo+ICB9Cj4gQEAgLTM5NzUsNyArMzk0MCw3IEBAIGludGVsX2RwX3Byb2Jl X21zdChzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwKQo+ICAJaWYgKGludGVsX2RwLT5kcGNkW0RQ X0RQQ0RfUkVWXSA8IDB4MTIpCj4gIAkJcmV0dXJuIGZhbHNlOwo+ICAKPiAtCWlmIChpbnRlbF9k cF9kcGNkX3JlYWRfd2FrZSgmaW50ZWxfZHAtPmF1eCwgRFBfTVNUTV9DQVAsIGJ1ZiwgMSkpIHsK PiArCWlmIChkcm1fZHBfZHBjZF9yZWFkKCZpbnRlbF9kcC0+YXV4LCBEUF9NU1RNX0NBUCwgYnVm LCAxKSkgewo+ICAJCWlmIChidWZbMF0gJiBEUF9NU1RfQ0FQKSB7Cj4gIAkJCURSTV9ERUJVR19L TVMoIlNpbmsgaXMgTVNUIGNhcGFibGVcbiIpOwo+ICAJCQlpbnRlbF9kcC0+aXNfbXN0ID0gdHJ1 ZTsKPiBAQCAtNDExMiw3ICs0MDc3LDcgQEAgc3RvcDoKPiAgc3RhdGljIGJvb2wKPiAgaW50ZWxf ZHBfZ2V0X3NpbmtfaXJxKHN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAsIHU4ICpzaW5rX2lycV92 ZWN0b3IpCj4gIHsKPiAtCXJldHVybiBpbnRlbF9kcF9kcGNkX3JlYWRfd2FrZSgmaW50ZWxfZHAt PmF1eCwKPiArCXJldHVybiBkcm1fZHBfZHBjZF9yZWFkKCZpbnRlbF9kcC0+YXV4LAo+ICAJCQkJ ICAgICAgIERQX0RFVklDRV9TRVJWSUNFX0lSUV9WRUNUT1IsCj4gIAkJCQkgICAgICAgc2lua19p cnFfdmVjdG9yLCAxKSA9PSAxOwo+ICB9Cj4gQEAgLTQxMjIsNyArNDA4Nyw3IEBAIGludGVsX2Rw X2dldF9zaW5rX2lycV9lc2koc3RydWN0IGludGVsX2RwICppbnRlbF9kcCwgdTggKnNpbmtfaXJx X3ZlY3RvcikKPiAgewo+ICAJaW50IHJldDsKPiAgCj4gLQlyZXQgPSBpbnRlbF9kcF9kcGNkX3Jl YWRfd2FrZSgmaW50ZWxfZHAtPmF1eCwKPiArCXJldCA9IGRybV9kcF9kcGNkX3JlYWQoJmludGVs X2RwLT5hdXgsCj4gIAkJCQkJICAgICBEUF9TSU5LX0NPVU5UX0VTSSwKPiAgCQkJCQkgICAgIHNp bmtfaXJxX3ZlY3RvciwgMTQpOwo+ICAJaWYgKHJldCAhPSAxNCkKPiBAQCAtNDM4Myw3ICs0MzQ4 LDcgQEAgaW50ZWxfZHBfZGV0ZWN0X2RwY2Qoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCkKPiAg CSAgICBpbnRlbF9kcC0+ZG93bnN0cmVhbV9wb3J0c1swXSAmIERQX0RTX1BPUlRfSFBEKSB7Cj4g IAkJdWludDhfdCByZWc7Cj4gIAo+IC0JCWlmIChpbnRlbF9kcF9kcGNkX3JlYWRfd2FrZSgmaW50 ZWxfZHAtPmF1eCwgRFBfU0lOS19DT1VOVCwKPiArCQlpZiAoZHJtX2RwX2RwY2RfcmVhZCgmaW50 ZWxfZHAtPmF1eCwgRFBfU0lOS19DT1VOVCwKPiAgCQkJCQkgICAgJnJlZywgMSkgPCAwKQo+ICAJ CQlyZXR1cm4gY29ubmVjdG9yX3N0YXR1c191bmtub3duOwo+ICAKPiAtLSAKPiAyLjUuMAo+IAo+ IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gSW50ZWwt Z2Z4IG1haWxpbmcgbGlzdAo+IEludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPiBodHRw czovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAoKLS0g ClZpbGxlIFN5cmrDpGzDpApJbnRlbCBPVEMKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMu ZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlz dGluZm8vaW50ZWwtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757358AbcCRON6 (ORCPT ); Fri, 18 Mar 2016 10:13:58 -0400 Received: from mga04.intel.com ([192.55.52.120]:16162 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933338AbcCRONy (ORCPT ); Fri, 18 Mar 2016 10:13:54 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,355,1455004800"; d="scan'208";a="671902089" Date: Fri, 18 Mar 2016 16:13:45 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Lyude Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, David Airlie , arthur.j.runyan@intel.com, open list , Daniel Vetter Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Get rid of intel_dp_dpcd_read_wake() Message-ID: <20160318141345.GG4329@intel.com> References: <1458229245-8634-1-git-send-email-cpaul@redhat.com> <1458229245-8634-2-git-send-email-cpaul@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1458229245-8634-2-git-send-email-cpaul@redhat.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 17, 2016 at 11:40:45AM -0400, Lyude wrote: > Since we've fixed up drm_dp_dpcd_read() to allow for retries when things > timeout, there's no use for having this function anymore. Good riddens. > > Signed-off-by: Lyude > --- > drivers/gpu/drm/i915/intel_dp.c | 79 ++++++++++++----------------------------- > 1 file changed, 22 insertions(+), 57 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index cdc2c15..fb4cbbe5 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3190,47 +3190,14 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder) > } > > /* > - * Native read with retry for link status and receiver capability reads for > - * cases where the sink may still be asleep. > - * > - * Sinks are *supposed* to come up within 1ms from an off state, but we're also > - * supposed to retry 3 times per the spec. > - */ > -static ssize_t > -intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, > - void *buffer, size_t size) > -{ > - ssize_t ret; > - int i; > - > - /* > - * Sometime we just get the same incorrect byte repeated > - * over the entire buffer. Doing just one throw away read > - * initially seems to "solve" it. > - */ > - drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); NAK If people keep intentionally breaking my shit I'm going to become really grumpy soon. > - > - for (i = 0; i < 3; i++) { > - ret = drm_dp_dpcd_read(aux, offset, buffer, size); > - if (ret == size) > - return ret; > - msleep(1); > - } > - > - return ret; > -} > - > -/* > * Fetch AUX CH registers 0x202 - 0x207 which contain > * link status information > */ > bool > intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) > { > - return intel_dp_dpcd_read_wake(&intel_dp->aux, > - DP_LANE0_1_STATUS, > - link_status, > - DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; > + return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, > + DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; > } > > /* These are source-specific values. */ > @@ -3865,8 +3832,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > struct drm_i915_private *dev_priv = dev->dev_private; > uint8_t rev; > > - if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, > - sizeof(intel_dp->dpcd)) < 0) > + if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, > + sizeof(intel_dp->dpcd)) < 0) > return false; /* aux transfer failed */ > > DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); > @@ -3877,9 +3844,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > /* Check if the panel supports PSR */ > memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); > if (is_edp(intel_dp)) { > - intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, > - intel_dp->psr_dpcd, > - sizeof(intel_dp->psr_dpcd)); > + drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, > + intel_dp->psr_dpcd, > + sizeof(intel_dp->psr_dpcd)); > if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { > dev_priv->psr.sink_support = true; > DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); > @@ -3890,9 +3857,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > uint8_t frame_sync_cap; > > dev_priv->psr.sink_support = true; > - intel_dp_dpcd_read_wake(&intel_dp->aux, > - DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, > - &frame_sync_cap, 1); > + drm_dp_dpcd_read(&intel_dp->aux, > + DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, > + &frame_sync_cap, 1); > dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; > /* PSR2 needs frame sync as well */ > dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; > @@ -3908,15 +3875,13 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > /* Intermediate frequency support */ > if (is_edp(intel_dp) && > (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && > - (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && > + (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && > (rev >= 0x03)) { /* eDp v1.4 or higher */ > __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; > int i; > > - intel_dp_dpcd_read_wake(&intel_dp->aux, > - DP_SUPPORTED_LINK_RATES, > - sink_rates, > - sizeof(sink_rates)); > + drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, > + sink_rates, sizeof(sink_rates)); > > for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { > int val = le16_to_cpu(sink_rates[i]); > @@ -3939,9 +3904,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) > return true; /* no per-port downstream info */ > > - if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, > - intel_dp->downstream_ports, > - DP_MAX_DOWNSTREAM_PORTS) < 0) > + if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, > + intel_dp->downstream_ports, > + DP_MAX_DOWNSTREAM_PORTS) < 0) > return false; /* downstream port status fetch failed */ > > return true; > @@ -3955,11 +3920,11 @@ intel_dp_probe_oui(struct intel_dp *intel_dp) > if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) > return; > > - if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) > + if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) > DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", > buf[0], buf[1], buf[2]); > > - if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) > + if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) > DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", > buf[0], buf[1], buf[2]); > } > @@ -3975,7 +3940,7 @@ intel_dp_probe_mst(struct intel_dp *intel_dp) > if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) > return false; > > - if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { > + if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { > if (buf[0] & DP_MST_CAP) { > DRM_DEBUG_KMS("Sink is MST capable\n"); > intel_dp->is_mst = true; > @@ -4112,7 +4077,7 @@ stop: > static bool > intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) > { > - return intel_dp_dpcd_read_wake(&intel_dp->aux, > + return drm_dp_dpcd_read(&intel_dp->aux, > DP_DEVICE_SERVICE_IRQ_VECTOR, > sink_irq_vector, 1) == 1; > } > @@ -4122,7 +4087,7 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) > { > int ret; > > - ret = intel_dp_dpcd_read_wake(&intel_dp->aux, > + ret = drm_dp_dpcd_read(&intel_dp->aux, > DP_SINK_COUNT_ESI, > sink_irq_vector, 14); > if (ret != 14) > @@ -4383,7 +4348,7 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp) > intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { > uint8_t reg; > > - if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, > + if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, > ®, 1) < 0) > return connector_status_unknown; > > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC