From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Cristina Ciocan <cristina.ciocan@intel.com>
Cc: mathias.nyman@linux.intel.com, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, irina.tirdea@intel.com,
octavian.purdila@intel.com
Subject: Re: [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures
Date: Wed, 30 Mar 2016 14:15:01 +0300 [thread overview]
Message-ID: <20160330111501.GS2099@lahna.fi.intel.com> (raw)
In-Reply-To: <1459171780-24856-2-git-send-email-cristina.ciocan@intel.com>
On Mon, Mar 28, 2016 at 04:29:35PM +0300, Cristina Ciocan wrote:
> +/* SCORE pins */
> +static const struct pinctrl_pin_desc byt_score_pins[] = {
> + PINCTRL_PIN(0, "SATA_GP[0]"), /* GPIOC_0 */
> + PINCTRL_PIN(1, "SATA_GP[1]"), /* GPIOC_1 */
Maybe we should call these "SATA_GP0" and "SATA_GP1" like we do in other
Intel pinctrl drivers?
Also I don't think /* GPIOC_1 */ is really useful comment as that can be
derived already from the pin number.
Otherwise this looks good.
next prev parent reply other threads:[~2016-03-30 11:15 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures Cristina Ciocan
2016-03-30 11:15 ` Mika Westerberg [this message]
2016-03-30 11:33 ` Cristina Ciocan
2016-03-30 11:42 ` Mika Westerberg
2016-03-28 13:29 ` [PATCH v2 2/6] pinctrl: baytrail: Add pin control operations Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 3/6] pinctrl: baytrail: Update gpio chip operations Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 4/6] pinctrl: baytrail: Update irq " Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 5/6] pinctrl: baytrail: Register pin control handling Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 6/6] pinctrl: baytrail: Add debounce configuration Cristina Ciocan
2016-03-30 14:45 ` [PATCH v2 0/6] Add pinctrl support for Baytrail Mika Westerberg
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