diff for duplicates of <20160404134237.GC402@leoy-linaro> diff --git a/a/1.txt b/N1/1.txt index bbfce4e..63669e0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ On Mon, Apr 04, 2016 at 01:21:00PM +0200, Linus Walleij wrote: -> On Mon, Apr 4, 2016 at 3:43 AM, Leo Yan <leo.yan@linaro.org> wrote: +> On Mon, Apr 4, 2016 at 3:43 AM, Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote: > > On Sun, Apr 03, 2016 at 09:23:42PM +0200, Linus Walleij wrote: -> >> On Sat, Apr 2, 2016 at 11:29 AM, Guodong Xu <guodong.xu@linaro.org> wrote: +> >> On Sat, Apr 2, 2016 at 11:29 AM, Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote: > > >> By chance the code in the driver will allow just one clock and > >> will then assume that both the bus to the timer and the timer @@ -37,7 +37,7 @@ Also have checked Hi6220's spec, there have no timer's dediated clock enabling bits. This is the reason before I only registered one clock. So according to you and Rob's comments, how about change as below? - dual_timer0: timer at f8008000 { + dual_timer0: timer@f8008000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xf8008000 0x0 0x1000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, @@ -50,3 +50,7 @@ So according to you and Rob's comments, how about change as below? Thanks, Leo Yan +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 388d22f..6f21932 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,16 +3,27 @@ "ref\0CACRpkdbWuKx6=aF5xW=3EKfuUf-MYM_EEnovyhBnOGVOeHyCmQ@mail.gmail.com\0" "ref\020160404014359.GA15178@leoy-linaro\0" "ref\0CACRpkdZ=_86Rhc+ei+3uE0dda9+onC8pQwosheMfEj4tOqmcDA@mail.gmail.com\0" - "From\0leo.yan@linaro.org (Leo Yan)\0" - "Subject\0[PATCH v2 02/16] arm64: dts: add sp804 timer node for Hi6220\0" + "ref\0CACRpkdZ=_86Rhc+ei+3uE0dda9+onC8pQwosheMfEj4tOqmcDA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Subject\0Re: [PATCH v2 02/16] arm64: dts: add sp804 timer node for Hi6220\0" "Date\0Mon, 4 Apr 2016 21:42:37 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Cc\0Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" + Xu Wei <xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org> + Arnd Bergmann <arnd.bergmann-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + " XinWei Kong <kong.kongxinwei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\0" "\00:1\0" "b\0" "On Mon, Apr 04, 2016 at 01:21:00PM +0200, Linus Walleij wrote:\n" - "> On Mon, Apr 4, 2016 at 3:43 AM, Leo Yan <leo.yan@linaro.org> wrote:\n" + "> On Mon, Apr 4, 2016 at 3:43 AM, Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:\n" "> > On Sun, Apr 03, 2016 at 09:23:42PM +0200, Linus Walleij wrote:\n" - "> >> On Sat, Apr 2, 2016 at 11:29 AM, Guodong Xu <guodong.xu@linaro.org> wrote:\n" + "> >> On Sat, Apr 2, 2016 at 11:29 AM, Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:\n" "> \n" "> >> By chance the code in the driver will allow just one clock and\n" "> >> will then assume that both the bus to the timer and the timer\n" @@ -48,7 +59,7 @@ "enabling bits. This is the reason before I only registered one clock.\n" "So according to you and Rob's comments, how about change as below?\n" "\n" - "\t\tdual_timer0: timer at f8008000 {\n" + "\t\tdual_timer0: timer@f8008000 {\n" "\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" "\t\t\treg = <0x0 0xf8008000 0x0 0x1000>;\n" "\t\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -60,6 +71,10 @@ "\t\t};\n" "\n" "Thanks,\n" - Leo Yan + "Leo Yan\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -f2b347be78b9665336b1f745c0c6f74f4967732602d7b4f0d230ab7809f7b48c +d4c5503fc26c93586842e3ebf803e74cb1c6e875c47c4d50a969c900dc0cdf63
diff --git a/a/1.txt b/N2/1.txt index bbfce4e..e3ecf3d 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -37,7 +37,7 @@ Also have checked Hi6220's spec, there have no timer's dediated clock enabling bits. This is the reason before I only registered one clock. So according to you and Rob's comments, how about change as below? - dual_timer0: timer at f8008000 { + dual_timer0: timer@f8008000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xf8008000 0x0 0x1000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, diff --git a/a/content_digest b/N2/content_digest index 388d22f..d8e9f82 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,10 +3,20 @@ "ref\0CACRpkdbWuKx6=aF5xW=3EKfuUf-MYM_EEnovyhBnOGVOeHyCmQ@mail.gmail.com\0" "ref\020160404014359.GA15178@leoy-linaro\0" "ref\0CACRpkdZ=_86Rhc+ei+3uE0dda9+onC8pQwosheMfEj4tOqmcDA@mail.gmail.com\0" - "From\0leo.yan@linaro.org (Leo Yan)\0" - "Subject\0[PATCH v2 02/16] arm64: dts: add sp804 timer node for Hi6220\0" + "From\0Leo Yan <leo.yan@linaro.org>\0" + "Subject\0Re: [PATCH v2 02/16] arm64: dts: add sp804 timer node for Hi6220\0" "Date\0Mon, 4 Apr 2016 21:42:37 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Linus Walleij <linus.walleij@linaro.org>\0" + "Cc\0Guodong Xu <guodong.xu@linaro.org>" + Xu Wei <xuwei5@hisilicon.com> + Mark Rutland <mark.rutland@arm.com> + Rob Herring <robh@kernel.org> + Grant Likely <grant.likely@secretlab.ca> + Arnd Bergmann <arnd.bergmann@linaro.org> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + " XinWei Kong <kong.kongxinwei@hisilicon.com>\0" "\00:1\0" "b\0" "On Mon, Apr 04, 2016 at 01:21:00PM +0200, Linus Walleij wrote:\n" @@ -48,7 +58,7 @@ "enabling bits. This is the reason before I only registered one clock.\n" "So according to you and Rob's comments, how about change as below?\n" "\n" - "\t\tdual_timer0: timer at f8008000 {\n" + "\t\tdual_timer0: timer@f8008000 {\n" "\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" "\t\t\treg = <0x0 0xf8008000 0x0 0x1000>;\n" "\t\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -62,4 +72,4 @@ "Thanks,\n" Leo Yan -f2b347be78b9665336b1f745c0c6f74f4967732602d7b4f0d230ab7809f7b48c +7459b6b1dc89109243afa24301ffd404401f5b74dd49500f6aa83e3f92a488ba
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