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diff for duplicates of <20160411112654.GC17743@ulmo.ba.sec>

diff --git a/a/1.txt b/N1/1.txt
index 4b8933f..9c47578 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -5,15 +5,15 @@ On Fri, Apr 08, 2016 at 02:11:42PM -0500, Bjorn Helgaas wrote:
 > DT-illiterate.
 > 
 > On Fri, Apr 08, 2016 at 06:13:13PM +0200, Thierry Reding wrote:
-> > From: Thierry Reding <treding@nvidia.com>
+> > From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
 > > 
 > > Changes to the pad controller device tree binding have required that
 > > each lane be associated with a separate PHY. Update the PCI host bridge
 > > device tree binding to allow each root port to define the list of PHYs
 > > required to drive the lanes associated with it.
 > > 
-> > Acked-by: Rob Herring <robh@kernel.org>
-> > Signed-off-by: Thierry Reding <treding@nvidia.com>
+> > Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
+> > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
 > > ---
 > > Changes in v4:
 > > - add additional lanes subnode when dereferencing PHYs from the XUSB pad
diff --git a/a/content_digest b/N1/content_digest
index 8e3d80f..d213c36 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,15 +1,15 @@
  "ref\01460131994-24493-1-git-send-email-thierry.reding@gmail.com\0"
  "ref\020160408191142.GD15034@localhost\0"
- "From\0Thierry Reding <thierry.reding@gmail.com>\0"
+ "From\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0"
  "Subject\0Re: [PATCH v4 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs\0"
  "Date\0Mon, 11 Apr 2016 13:26:54 +0200\0"
- "To\0Bjorn Helgaas <helgaas@kernel.org>\0"
- "Cc\0Bjorn Helgaas <bhelgaas@google.com>"
-  Stephen Warren <swarren@wwwdotorg.org>
-  Alexandre Courbot <gnurou@gmail.com>
-  linux-tegra@vger.kernel.org
-  linux-pci@vger.kernel.org
- " devicetree@vger.kernel.org\0"
+ "To\0Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0"
+ "Cc\0Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>"
+  Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
+  Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+  linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+  linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+ " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0"
  "\01:1\0"
  "b\0"
  "On Fri, Apr 08, 2016 at 02:11:42PM -0500, Bjorn Helgaas wrote:\n"
@@ -19,15 +19,15 @@
  "> DT-illiterate.\n"
  "> \n"
  "> On Fri, Apr 08, 2016 at 06:13:13PM +0200, Thierry Reding wrote:\n"
- "> > From: Thierry Reding <treding@nvidia.com>\n"
+ "> > From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n"
  "> > \n"
  "> > Changes to the pad controller device tree binding have required that\n"
  "> > each lane be associated with a separate PHY. Update the PCI host bridge\n"
  "> > device tree binding to allow each root port to define the list of PHYs\n"
  "> > required to drive the lanes associated with it.\n"
  "> > \n"
- "> > Acked-by: Rob Herring <robh@kernel.org>\n"
- "> > Signed-off-by: Thierry Reding <treding@nvidia.com>\n"
+ "> > Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\n"
+ "> > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n"
  "> > ---\n"
  "> > Changes in v4:\n"
  "> > - add additional lanes subnode when dereferencing PHYs from the XUSB pad\n"
@@ -175,4 +175,4 @@
  "=40DO\n"
  "-----END PGP SIGNATURE-----\n"
 
-4d208aaa5b3a1f030bc84ede9127f39cd304d5de3f4a868afa7a0d80afd7470a
+f01b3091072523f6e0bcb8c477813542d556730cf601adf1eff5408a338da09c

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