From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings
Date: Mon, 11 Apr 2016 11:00:53 -0400 [thread overview]
Message-ID: <20160411150053.GC13577@bill-the-cat> (raw)
In-Reply-To: <1460152424-30181-1-git-send-email-nm@ti.com>
On Fri, Apr 08, 2016 at 04:53:44PM -0500, Nishanth Menon wrote:
> From: Schuyler Patton <spatton@ti.com>
>
> Update EMIF data based on recommendations from the now standard TI
> EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
> data sheet
>
> Update T_RRD from 5 to 6 based on AM57xx TRM -
> Minimum number of DDR cycles from activate to ativate for a different
> bank, minus 1.
>
> Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
> clocks cycles for which SDRAM must remain in self refresh, minus 1.
>
> Signed-off-by: Schuyler Patton <spatton@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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next prev parent reply other threads:[~2016-04-11 15:00 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-08 21:53 [U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings Nishanth Menon
2016-04-11 5:19 ` Lokesh Vutla
2016-04-11 15:00 ` Tom Rini [this message]
2016-04-21 11:21 ` [U-Boot] " Tom Rini
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