From mboxrd@z Thu Jan 1 00:00:00 1970 From: shawnguo@kernel.org (Shawn Guo) Date: Tue, 12 Apr 2016 09:38:21 +0800 Subject: [PATCH v3 1/9] ARM: imx: clk-vf610: fix DCU clock tree In-Reply-To: <1459834121-25997-2-git-send-email-stefan@agner.ch> References: <1459834121-25997-1-git-send-email-stefan@agner.ch> <1459834121-25997-2-git-send-email-stefan@agner.ch> Message-ID: <20160412013820.GC15949@tiger> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Apr 04, 2016 at 10:28:33PM -0700, Stefan Agner wrote: > Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy > mixes the bus clock with the display controllers pixel clock. Tests > have shown that the gates in CCM_CCGR3/9 registers do not control > the DCU pixel clock, but only the register access clock (bus clock). > > Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus > clock (ipg_bus). > > Since the clock has not been used far, there are no further changes > needed. > > Signed-off-by: Stefan Agner Applied 1 and 2, with updating subject prefix to be 'clk: imx: vf610: ' Shawn > --- > drivers/clk/imx/clk-vf610.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c > index 0a94d96..426fde2 100644 > --- a/drivers/clk/imx/clk-vf610.c > +++ b/drivers/clk/imx/clk-vf610.c > @@ -321,11 +321,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) > clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); > clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); > clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); > - clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); > + clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "ipg_bus", CCM_CCGR3, CCM_CCGRx_CGn(8)); > clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); > clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); > clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); > - clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); > + clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8)); > > clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); > clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); > -- > 2.7.4 > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH v3 1/9] ARM: imx: clk-vf610: fix DCU clock tree Date: Tue, 12 Apr 2016 09:38:21 +0800 Message-ID: <20160412013820.GC15949@tiger> References: <1459834121-25997-1-git-send-email-stefan@agner.ch> <1459834121-25997-2-git-send-email-stefan@agner.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1459834121-25997-2-git-send-email-stefan@agner.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Stefan Agner Cc: jianwei.wang.chn@gmail.com, meng.yi@nxp.com, pawel.moll@arm.com, alison.wang@freescale.com, daniel.vetter@ffwll.ch, mturquette@baylibre.com, ijc+devicetree@hellion.org.uk, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, robh+dt@kernel.org, kernel@pengutronix.de, galak@codeaurora.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, alexander.stein@systec-electronic.com List-Id: devicetree@vger.kernel.org T24gTW9uLCBBcHIgMDQsIDIwMTYgYXQgMTA6Mjg6MzNQTSAtMDcwMCwgU3RlZmFuIEFnbmVyIHdy b3RlOgo+IFNpbWlsYXIgdG8gYW4gZWFybGllciBmaXggZm9yIHRoZSBTQUkgY2xvY2tzLCB0aGUg RENVIGNsb2NrIGhpZXJhcmNoeQo+IG1peGVzIHRoZSBidXMgY2xvY2sgd2l0aCB0aGUgZGlzcGxh eSBjb250cm9sbGVycyBwaXhlbCBjbG9jay4gVGVzdHMKPiBoYXZlIHNob3duIHRoYXQgdGhlIGdh dGVzIGluIENDTV9DQ0dSMy85IHJlZ2lzdGVycyBkbyBub3QgY29udHJvbAo+IHRoZSBEQ1UgcGl4 ZWwgY2xvY2ssIGJ1dCBvbmx5IHRoZSByZWdpc3RlciBhY2Nlc3MgY2xvY2sgKGJ1cyBjbG9jayku Cj4gCj4gRml4IHRoaXMgYnkgZGVmaW5pbmcgdGhlIHBhcmVudCBjbG9jayBvZiBWRjYxMF9DTEtf RENVeCB0byBiZSB0aGUgYnVzCj4gY2xvY2sgKGlwZ19idXMpLgo+IAo+IFNpbmNlIHRoZSBjbG9j ayBoYXMgbm90IGJlZW4gdXNlZCBmYXIsIHRoZXJlIGFyZSBubyBmdXJ0aGVyIGNoYW5nZXMKPiBu ZWVkZWQuCj4gCj4gU2lnbmVkLW9mZi1ieTogU3RlZmFuIEFnbmVyIDxzdGVmYW5AYWduZXIuY2g+ CgpBcHBsaWVkIDEgYW5kIDIsIHdpdGggdXBkYXRpbmcgc3ViamVjdCBwcmVmaXggdG8gYmUgJ2Ns azogaW14OiB2ZjYxMDogJwoKU2hhd24KCj4gLS0tCj4gIGRyaXZlcnMvY2xrL2lteC9jbGstdmY2 MTAuYyB8IDQgKystLQo+ICAxIGZpbGUgY2hhbmdlZCwgMiBpbnNlcnRpb25zKCspLCAyIGRlbGV0 aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Nsay9pbXgvY2xrLXZmNjEwLmMgYi9k cml2ZXJzL2Nsay9pbXgvY2xrLXZmNjEwLmMKPiBpbmRleCAwYTk0ZDk2Li40MjZmZGUyIDEwMDY0 NAo+IC0tLSBhL2RyaXZlcnMvY2xrL2lteC9jbGstdmY2MTAuYwo+ICsrKyBiL2RyaXZlcnMvY2xr L2lteC9jbGstdmY2MTAuYwo+IEBAIC0zMjEsMTEgKzMyMSwxMSBAQCBzdGF0aWMgdm9pZCBfX2lu aXQgdmY2MTBfY2xvY2tzX2luaXQoc3RydWN0IGRldmljZV9ub2RlICpjY21fbm9kZSkKPiAgCWNs a1tWRjYxMF9DTEtfRENVMF9TRUxdID0gaW14X2Nsa19tdXgoImRjdTBfc2VsIiwgQ0NNX0NTQ01S MSwgMjgsIDEsIGRjdV9zZWxzLCAyKTsKPiAgCWNsa1tWRjYxMF9DTEtfRENVMF9FTl0gPSBpbXhf Y2xrX2dhdGUoImRjdTBfZW4iLCAiZGN1MF9zZWwiLCBDQ01fQ1NDRFIzLCAxOSk7Cj4gIAljbGtb VkY2MTBfQ0xLX0RDVTBfRElWXSA9IGlteF9jbGtfZGl2aWRlcigiZGN1MF9kaXYiLCAiZGN1MF9l biIsIENDTV9DU0NEUjMsIDE2LCAzKTsKPiAtCWNsa1tWRjYxMF9DTEtfRENVMF0gPSBpbXhfY2xr X2dhdGUyKCJkY3UwIiwgImRjdTBfZGl2IiwgQ0NNX0NDR1IzLCBDQ01fQ0NHUnhfQ0duKDgpKTsK PiArCWNsa1tWRjYxMF9DTEtfRENVMF0gPSBpbXhfY2xrX2dhdGUyKCJkY3UwIiwgImlwZ19idXMi LCBDQ01fQ0NHUjMsIENDTV9DQ0dSeF9DR24oOCkpOwo+ICAJY2xrW1ZGNjEwX0NMS19EQ1UxX1NF TF0gPSBpbXhfY2xrX211eCgiZGN1MV9zZWwiLCBDQ01fQ1NDTVIxLCAyOSwgMSwgZGN1X3NlbHMs IDIpOwo+ICAJY2xrW1ZGNjEwX0NMS19EQ1UxX0VOXSA9IGlteF9jbGtfZ2F0ZSgiZGN1MV9lbiIs ICJkY3UxX3NlbCIsIENDTV9DU0NEUjMsIDIzKTsKPiAgCWNsa1tWRjYxMF9DTEtfRENVMV9ESVZd ID0gaW14X2Nsa19kaXZpZGVyKCJkY3UxX2RpdiIsICJkY3UxX2VuIiwgQ0NNX0NTQ0RSMywgMjAs IDMpOwo+IC0JY2xrW1ZGNjEwX0NMS19EQ1UxXSA9IGlteF9jbGtfZ2F0ZTIoImRjdTEiLCAiZGN1 MV9kaXYiLCBDQ01fQ0NHUjksIENDTV9DQ0dSeF9DR24oOCkpOwo+ICsJY2xrW1ZGNjEwX0NMS19E Q1UxXSA9IGlteF9jbGtfZ2F0ZTIoImRjdTEiLCAiaXBnX2J1cyIsIENDTV9DQ0dSOSwgQ0NNX0ND R1J4X0NHbig4KSk7Cj4gIAo+ICAJY2xrW1ZGNjEwX0NMS19FU0FJX1NFTF0gPSBpbXhfY2xrX211 eCgiZXNhaV9zZWwiLCBDQ01fQ1NDTVIxLCAyMCwgMiwgZXNhaV9zZWxzLCA0KTsKPiAgCWNsa1tW RjYxMF9DTEtfRVNBSV9FTl0gPSBpbXhfY2xrX2dhdGUoImVzYWlfZW4iLCAiZXNhaV9zZWwiLCBD Q01fQ1NDRFIyLCAzMCk7Cj4gLS0gCj4gMi43LjQKPiAKPiAKX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2 ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21h aWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755594AbcDLBiw (ORCPT ); Mon, 11 Apr 2016 21:38:52 -0400 Received: from mail.kernel.org ([198.145.29.136]:58055 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753804AbcDLBiu (ORCPT ); Mon, 11 Apr 2016 21:38:50 -0400 Date: Tue, 12 Apr 2016 09:38:21 +0800 From: Shawn Guo To: Stefan Agner Cc: dri-devel@lists.freedesktop.org, kernel@pengutronix.de, airlied@linux.ie, daniel.vetter@ffwll.ch, jianwei.wang.chn@gmail.com, alison.wang@freescale.com, meng.yi@nxp.com, alexander.stein@systec-electronic.com, mturquette@baylibre.com, sboyd@codeaurora.org, mark.rutland@arm.com, robh+dt@kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 1/9] ARM: imx: clk-vf610: fix DCU clock tree Message-ID: <20160412013820.GC15949@tiger> References: <1459834121-25997-1-git-send-email-stefan@agner.ch> <1459834121-25997-2-git-send-email-stefan@agner.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1459834121-25997-2-git-send-email-stefan@agner.ch> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 04, 2016 at 10:28:33PM -0700, Stefan Agner wrote: > Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy > mixes the bus clock with the display controllers pixel clock. Tests > have shown that the gates in CCM_CCGR3/9 registers do not control > the DCU pixel clock, but only the register access clock (bus clock). > > Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus > clock (ipg_bus). > > Since the clock has not been used far, there are no further changes > needed. > > Signed-off-by: Stefan Agner Applied 1 and 2, with updating subject prefix to be 'clk: imx: vf610: ' Shawn > --- > drivers/clk/imx/clk-vf610.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c > index 0a94d96..426fde2 100644 > --- a/drivers/clk/imx/clk-vf610.c > +++ b/drivers/clk/imx/clk-vf610.c > @@ -321,11 +321,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) > clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); > clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); > clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); > - clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); > + clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "ipg_bus", CCM_CCGR3, CCM_CCGRx_CGn(8)); > clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); > clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); > clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); > - clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); > + clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8)); > > clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); > clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); > -- > 2.7.4 > >