From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 19 Apr 2016 11:18:23 +0200 Subject: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock In-Reply-To: <20160415223441.GT14441@codeaurora.org> References: <1458751122-23976-1-git-send-email-maxime.ripard@free-electrons.com> <1458751122-23976-4-git-send-email-maxime.ripard@free-electrons.com> <20160415223441.GT14441@codeaurora.org> Message-ID: <20160419091823.GX4005@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > > PLL7, clocked from a 3MHz oscillator, that drives the display related > > clocks (GPU, display engine, TCON, etc.) > > > > Add a driver for it. > > > > Acked-by: Rob Herring > > Acked-by: Chen-Yu Tsai > > Signed-off-by: Maxime Ripard > > --- > > Acked-by: Stephen Boyd Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock Date: Tue, 19 Apr 2016 11:18:23 +0200 Message-ID: <20160419091823.GX4005@lukather> References: <1458751122-23976-1-git-send-email-maxime.ripard@free-electrons.com> <1458751122-23976-4-git-send-email-maxime.ripard@free-electrons.com> <20160415223441.GT14441@codeaurora.org> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Y46NoIcKQuicSz3X" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20160415223441.GT14441-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Stephen Boyd Cc: Mike Turquette , David Airlie , Thierry Reding , Rob Herring , Chen-Yu Tsai , Daniel Vetter , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Laurent Pinchart , Hans de Goede , Alexander Kaplan , Boris Brezillon , Thomas Petazzoni , Rob Clark List-Id: devicetree@vger.kernel.org --Y46NoIcKQuicSz3X Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > > PLL7, clocked from a 3MHz oscillator, that drives the display related > > clocks (GPU, display engine, TCON, etc.) > > > > Add a driver for it. > > > > Acked-by: Rob Herring > > Acked-by: Chen-Yu Tsai > > Signed-off-by: Maxime Ripard > > --- > > Acked-by: Stephen Boyd Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --Y46NoIcKQuicSz3X-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753456AbcDSJSh (ORCPT ); Tue, 19 Apr 2016 05:18:37 -0400 Received: from down.free-electrons.com ([37.187.137.238]:43491 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753378AbcDSJSf (ORCPT ); Tue, 19 Apr 2016 05:18:35 -0400 Date: Tue, 19 Apr 2016 11:18:23 +0200 From: Maxime Ripard To: Stephen Boyd Cc: Mike Turquette , David Airlie , Thierry Reding , Rob Herring , Chen-Yu Tsai , Daniel Vetter , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, Laurent Pinchart , Hans de Goede , Alexander Kaplan , Boris Brezillon , Thomas Petazzoni , Rob Clark Subject: Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock Message-ID: <20160419091823.GX4005@lukather> References: <1458751122-23976-1-git-send-email-maxime.ripard@free-electrons.com> <1458751122-23976-4-git-send-email-maxime.ripard@free-electrons.com> <20160415223441.GT14441@codeaurora.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Y46NoIcKQuicSz3X" Content-Disposition: inline In-Reply-To: <20160415223441.GT14441@codeaurora.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Y46NoIcKQuicSz3X Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > > PLL7, clocked from a 3MHz oscillator, that drives the display related > > clocks (GPU, display engine, TCON, etc.) > >=20 > > Add a driver for it. > >=20 > > Acked-by: Rob Herring > > Acked-by: Chen-Yu Tsai > > Signed-off-by: Maxime Ripard > > --- >=20 > Acked-by: Stephen Boyd Applied, thanks! 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