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From: Jim Bride <jim.bride@linux.intel.com>
To: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 08/10] drm/i915: Unduplicate VLV phy pre pll enabling code
Date: Wed, 20 Apr 2016 12:50:37 -0700	[thread overview]
Message-ID: <20160420195037.GG13777@shiv> (raw)
In-Reply-To: <1460569673-13694-9-git-send-email-ander.conselvan.de.oliveira@intel.com>

On Wed, Apr 13, 2016 at 08:47:51PM +0300, Ander Conselvan de Oliveira wrote:
> The code used by the DP and HDMI paths was very similar, so make them
> share it. Note that this removes the write to signal level registers
> from the HDMI pre pll enable path, but that's OK since those are set
> in vlv_hdmi_pre_enable() function.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_dp.c       | 25 +------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 28 ++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 28 +---------------------------
>  4 files changed, 31 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f2481a2..a002870 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3568,6 +3568,7 @@ void chv_phy_post_disable(struct intel_encoder *encoder);
>  void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      u32 demph_reg_value, u32 preemph_reg_value,
>  			      u32 uniqtranscale_reg_value, u32 tx3_demph);
> +void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3e42355..4829ba9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2821,32 +2821,9 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
>  
>  static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  {
> -	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -
>  	intel_dp_prepare(encoder);
>  
> -	/* Program Tx lane resets to default */
> -	mutex_lock(&dev_priv->sb_lock);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> -			 DPIO_PCS_TX_LANE2_RESET |
> -			 DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> -			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> -			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> -			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> -				 DPIO_PCS_CLK_SOFT_RESET);
> -
> -	/* Fix up inter-pair skew failure */
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_phy_pre_pll_enable(encoder);
>  }
>  
>  static void chv_pre_enable_dp(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index d9e6482..846f35f 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -395,3 +395,31 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
> +
> +void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel port = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +
> +	/* Program Tx lane resets to default */
> +	mutex_lock(&dev_priv->sb_lock);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> +			 DPIO_PCS_TX_LANE2_RESET |
> +			 DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> +			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> +			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> +			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> +				 DPIO_PCS_CLK_SOFT_RESET);
> +
> +	/* Fix up inter-pair skew failure */
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9386772..f0c21e4 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1621,35 +1621,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
>  
>  static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  {
> -	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -
>  	intel_hdmi_prepare(encoder);
>  
> -	/* Program Tx lane resets to default */
> -	mutex_lock(&dev_priv->sb_lock);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> -			 DPIO_PCS_TX_LANE2_RESET |
> -			 DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> -			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> -			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> -			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> -			 DPIO_PCS_CLK_SOFT_RESET);
> -
> -	/* Fix up inter-pair skew failure */
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> -
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_phy_pre_pll_enable(encoder);
>  }
>  
>  static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> -- 
> 2.4.11
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2016-04-20 19:50 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-13 17:47 [PATCH v2 00/10] Unduplicate CHV phy code Ander Conselvan de Oliveira
2016-04-13 17:47 ` [PATCH v2 01/10] drm/i915: Set crtc_state->lane_count for HDMI Ander Conselvan de Oliveira
2016-04-19 20:40   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 02/10] drm/i915: Unduplicate CHV signal level code Ander Conselvan de Oliveira
2016-04-20 19:13   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 03/10] drm/i915: Unduplicate chv_data_lane_soft_reset() Ander Conselvan de Oliveira
2016-04-20 19:24   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 04/10] drm/i915: Unduplicate CHV phy-releated pre pll enabling code Ander Conselvan de Oliveira
2016-04-20 19:45   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 05/10] drm/i915: Unduplicate CHV pre-encoder enabling phy logic Ander Conselvan de Oliveira
2016-04-20 19:48   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 06/10] drm/i915: Undiplicate CHV encoders' post pll disable code Ander Conselvan de Oliveira
2016-04-19 20:42   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code Ander Conselvan de Oliveira
2016-04-19 20:37   ` Jim Bride
2016-04-19 20:45     ` Jim Bride
2016-04-20  5:23     ` Conselvan De Oliveira, Ander
2016-04-13 17:47 ` [PATCH v2 08/10] drm/i915: Unduplicate VLV phy pre pll enabling code Ander Conselvan de Oliveira
2016-04-20 19:50   ` Jim Bride [this message]
2016-04-13 17:47 ` [PATCH v2 09/10] drm/i915: Unduplicate pre encoder enabling phy code Ander Conselvan de Oliveira
2016-04-20 19:52   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 10/10] drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.c Ander Conselvan de Oliveira
2016-04-20 19:53   ` Jim Bride
2016-04-14 13:03 ` ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev3) Patchwork
2016-04-20  5:20 ` [PATCH v2 06/18] drm/i915: Unduplicate CHV encoders' post pll disable code Ander Conselvan de Oliveira
2016-04-20 17:20   ` Jim Bride
2016-04-20  5:22 ` [PATCH v2 07/18] drm/i915: Undiplicate VLV signal level code Ander Conselvan de Oliveira
2016-04-20 18:01   ` Jim Bride

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